Lines Matching refs:gmc
196 adev->gmc.vm_fault.num_types = 1; in gmc_v10_0_set_irq_funcs()
197 adev->gmc.vm_fault.funcs = &gmc_v10_0_irq_funcs; in gmc_v10_0_set_irq_funcs()
200 adev->gmc.ecc_irq.num_types = 1; in gmc_v10_0_set_irq_funcs()
201 adev->gmc.ecc_irq.funcs = &gmc_v10_0_ecc_funcs; in gmc_v10_0_set_irq_funcs()
255 spin_lock(&adev->gmc.invalidate_lock); in gmc_v10_0_flush_vm_hub()
313 spin_unlock(&adev->gmc.invalidate_lock); in gmc_v10_0_flush_vm_hub()
603 if (!adev->gmc.translate_further) in gmc_v10_0_get_vm_pde()
683 if (adev->gmc.gmc_funcs == NULL) in gmc_v10_0_set_gmc_funcs()
684 adev->gmc.gmc_funcs = &gmc_v10_0_gmc_funcs; in gmc_v10_0_set_gmc_funcs()
766 adev->gmc.shared_aperture_start = 0x2000000000000000ULL; in gmc_v10_0_early_init()
767 adev->gmc.shared_aperture_end = in gmc_v10_0_early_init()
768 adev->gmc.shared_aperture_start + (4ULL << 30) - 1; in gmc_v10_0_early_init()
769 adev->gmc.private_aperture_start = 0x1000000000000000ULL; in gmc_v10_0_early_init()
770 adev->gmc.private_aperture_end = in gmc_v10_0_early_init()
771 adev->gmc.private_aperture_start + (4ULL << 30) - 1; in gmc_v10_0_early_init()
793 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); in gmc_v10_0_late_init()
804 base += adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; in gmc_v10_0_vram_gtt_location()
806 amdgpu_gmc_vram_location(adev, &adev->gmc, base); in gmc_v10_0_vram_gtt_location()
815 adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; in gmc_v10_0_vram_gtt_location()
832 adev->gmc.mc_vram_size = in gmc_v10_0_mc_init()
834 adev->gmc.real_vram_size = adev->gmc.mc_vram_size; in gmc_v10_0_mc_init()
841 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); in gmc_v10_0_mc_init()
842 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); in gmc_v10_0_mc_init()
846 adev->gmc.aper_base = adev->gfxhub.funcs->get_mc_fb_offset(adev); in gmc_v10_0_mc_init()
847 adev->gmc.aper_size = adev->gmc.real_vram_size; in gmc_v10_0_mc_init()
851 adev->gmc.visible_vram_size = adev->gmc.aper_size; in gmc_v10_0_mc_init()
857 adev->gmc.gart_size = 512ULL << 20; in gmc_v10_0_mc_init()
863 adev->gmc.gart_size = 1024ULL << 20; in gmc_v10_0_mc_init()
867 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; in gmc_v10_0_mc_init()
870 gmc_v10_0_vram_gtt_location(adev, &adev->gmc); in gmc_v10_0_mc_init()
905 spin_lock_init(&adev->gmc.invalidate_lock); in gmc_v10_0_sw_init()
908 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_DDR4; in gmc_v10_0_sw_init()
909 adev->gmc.vram_width = 64; in gmc_v10_0_sw_init()
911 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_GDDR6; in gmc_v10_0_sw_init()
912 adev->gmc.vram_width = 1 * 128; /* numchan * chansize */ in gmc_v10_0_sw_init()
916 adev->gmc.vram_width = vram_width; in gmc_v10_0_sw_init()
918 adev->gmc.vram_type = vram_type; in gmc_v10_0_sw_init()
919 adev->gmc.vram_vendor = vram_vendor; in gmc_v10_0_sw_init()
924 adev->gmc.mall_size = 128 * 1024 * 1024; in gmc_v10_0_sw_init()
927 adev->gmc.mall_size = 96 * 1024 * 1024; in gmc_v10_0_sw_init()
930 adev->gmc.mall_size = 32 * 1024 * 1024; in gmc_v10_0_sw_init()
933 adev->gmc.mall_size = 16 * 1024 * 1024; in gmc_v10_0_sw_init()
936 adev->gmc.mall_size = 0; in gmc_v10_0_sw_init()
969 &adev->gmc.vm_fault); in gmc_v10_0_sw_init()
976 &adev->gmc.vm_fault); in gmc_v10_0_sw_init()
983 &adev->gmc.ecc_irq); in gmc_v10_0_sw_init()
992 adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */ in gmc_v10_0_sw_init()
1101 (unsigned)(adev->gmc.gart_size >> 20), in gmc_v10_0_gart_enable()
1164 amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0); in gmc_v10_0_hw_fini()
1165 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); in gmc_v10_0_hw_fini()