Lines Matching refs:umc
691 adev->umc.max_ras_err_cnt_per_query = UMC_V8_7_TOTAL_CHANNEL_NUM; in gmc_v10_0_set_umc_funcs()
692 adev->umc.channel_inst_num = UMC_V8_7_CHANNEL_INSTANCE_NUM; in gmc_v10_0_set_umc_funcs()
693 adev->umc.umc_inst_num = UMC_V8_7_UMC_INSTANCE_NUM; in gmc_v10_0_set_umc_funcs()
694 adev->umc.channel_offs = UMC_V8_7_PER_CHANNEL_OFFSET_SIENNA; in gmc_v10_0_set_umc_funcs()
695 adev->umc.retire_unit = 1; in gmc_v10_0_set_umc_funcs()
696 adev->umc.channel_idx_tbl = &umc_v8_7_channel_idx_tbl[0][0]; in gmc_v10_0_set_umc_funcs()
697 adev->umc.ras = &umc_v8_7_ras; in gmc_v10_0_set_umc_funcs()
702 if (adev->umc.ras) { in gmc_v10_0_set_umc_funcs()
703 amdgpu_ras_register_ras_block(adev, &adev->umc.ras->ras_block); in gmc_v10_0_set_umc_funcs()
705 strcpy(adev->umc.ras->ras_block.ras_comm.name, "umc"); in gmc_v10_0_set_umc_funcs()
706 adev->umc.ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__UMC; in gmc_v10_0_set_umc_funcs()
707 adev->umc.ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; in gmc_v10_0_set_umc_funcs()
708 adev->umc.ras_if = &adev->umc.ras->ras_block.ras_comm; in gmc_v10_0_set_umc_funcs()
711 if (!adev->umc.ras->ras_block.ras_late_init) in gmc_v10_0_set_umc_funcs()
712 adev->umc.ras->ras_block.ras_late_init = amdgpu_umc_ras_late_init; in gmc_v10_0_set_umc_funcs()
715 if (!adev->umc.ras->ras_block.ras_cb) in gmc_v10_0_set_umc_funcs()
716 adev->umc.ras->ras_block.ras_cb = amdgpu_umc_process_ras_data_cb; in gmc_v10_0_set_umc_funcs()
1132 if (adev->umc.funcs && adev->umc.funcs->init_registers) in gmc_v10_0_hw_init()
1133 adev->umc.funcs->init_registers(adev); in gmc_v10_0_hw_init()