Lines Matching refs:umc
568 adev->umc.channel_inst_num = UMC_V8_10_CHANNEL_INSTANCE_NUM; in gmc_v11_0_set_umc_funcs()
569 adev->umc.umc_inst_num = UMC_V8_10_UMC_INSTANCE_NUM; in gmc_v11_0_set_umc_funcs()
570 adev->umc.max_ras_err_cnt_per_query = UMC_V8_10_TOTAL_CHANNEL_NUM(adev); in gmc_v11_0_set_umc_funcs()
571 adev->umc.channel_offs = UMC_V8_10_PER_CHANNEL_OFFSET; in gmc_v11_0_set_umc_funcs()
572 adev->umc.retire_unit = UMC_V8_10_NA_COL_2BITS_POWER_OF_2_NUM; in gmc_v11_0_set_umc_funcs()
573 if (adev->umc.node_inst_num == 4) in gmc_v11_0_set_umc_funcs()
574 adev->umc.channel_idx_tbl = &umc_v8_10_channel_idx_tbl_ext0[0][0][0]; in gmc_v11_0_set_umc_funcs()
576 adev->umc.channel_idx_tbl = &umc_v8_10_channel_idx_tbl[0][0][0]; in gmc_v11_0_set_umc_funcs()
577 adev->umc.ras = &umc_v8_10_ras; in gmc_v11_0_set_umc_funcs()
585 if (adev->umc.ras) { in gmc_v11_0_set_umc_funcs()
586 amdgpu_ras_register_ras_block(adev, &adev->umc.ras->ras_block); in gmc_v11_0_set_umc_funcs()
588 strcpy(adev->umc.ras->ras_block.ras_comm.name, "umc"); in gmc_v11_0_set_umc_funcs()
589 adev->umc.ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__UMC; in gmc_v11_0_set_umc_funcs()
590 adev->umc.ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; in gmc_v11_0_set_umc_funcs()
591 adev->umc.ras_if = &adev->umc.ras->ras_block.ras_comm; in gmc_v11_0_set_umc_funcs()
594 if (!adev->umc.ras->ras_block.ras_late_init) in gmc_v11_0_set_umc_funcs()
595 adev->umc.ras->ras_block.ras_late_init = amdgpu_umc_ras_late_init; in gmc_v11_0_set_umc_funcs()
598 if (!adev->umc.ras->ras_block.ras_cb) in gmc_v11_0_set_umc_funcs()
599 adev->umc.ras->ras_block.ras_cb = amdgpu_umc_process_ras_data_cb; in gmc_v11_0_set_umc_funcs()
929 if (adev->umc.funcs && adev->umc.funcs->init_registers) in gmc_v11_0_hw_init()
930 adev->umc.funcs->init_registers(adev); in gmc_v11_0_hw_init()