Lines Matching refs:vmid
128 entry->src_id, entry->ring_id, entry->vmid, in gmc_v11_0_process_interrupt()
177 uint8_t vmid, uint16_t *p_pasid) in gmc_v11_0_get_vmid_pasid_mapping_info() argument
179 *p_pasid = RREG32(SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT) + vmid) & 0xffff; in gmc_v11_0_get_vmid_pasid_mapping_info()
191 static void gmc_v11_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid, in gmc_v11_0_flush_vm_hub() argument
196 u32 inv_req = hub->vmhub_funcs->get_invalidate_req(vmid, flush_type); in gmc_v11_0_flush_vm_hub()
235 tmp &= 1 << vmid; in gmc_v11_0_flush_vm_hub()
280 static void gmc_v11_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, in gmc_v11_0_flush_gpu_tlb() argument
296 u32 inv_req = hub->vmhub_funcs->get_invalidate_req(vmid, flush_type); in gmc_v11_0_flush_gpu_tlb()
301 1 << vmid); in gmc_v11_0_flush_gpu_tlb()
306 gmc_v11_0_flush_vm_hub(adev, vmid, vmhub, 0); in gmc_v11_0_flush_gpu_tlb()
323 int vmid, i; in gmc_v11_0_flush_gpu_tlb_pasid() local
355 for (vmid = 1; vmid < 16; vmid++) { in gmc_v11_0_flush_gpu_tlb_pasid()
357 ret = gmc_v11_0_get_vmid_pasid_mapping_info(adev, vmid, in gmc_v11_0_flush_gpu_tlb_pasid()
362 gmc_v11_0_flush_gpu_tlb(adev, vmid, in gmc_v11_0_flush_gpu_tlb_pasid()
365 gmc_v11_0_flush_gpu_tlb(adev, vmid, in gmc_v11_0_flush_gpu_tlb_pasid()
375 unsigned vmid, uint64_t pd_addr) in gmc_v11_0_emit_flush_gpu_tlb() argument
379 uint32_t req = hub->vmhub_funcs->get_invalidate_req(vmid, 0); in gmc_v11_0_emit_flush_gpu_tlb()
397 (hub->ctx_addr_distance * vmid), in gmc_v11_0_emit_flush_gpu_tlb()
401 (hub->ctx_addr_distance * vmid), in gmc_v11_0_emit_flush_gpu_tlb()
408 req, 1 << vmid); in gmc_v11_0_emit_flush_gpu_tlb()
422 static void gmc_v11_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid, in gmc_v11_0_emit_pasid_mapping() argument
433 reg = SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT) + vmid; in gmc_v11_0_emit_pasid_mapping()
435 reg = SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT_MM) + vmid; in gmc_v11_0_emit_pasid_mapping()