Lines Matching refs:tmp
200 u32 tmp; in gmc_v8_0_mc_resume() local
203 tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL); in gmc_v8_0_mc_resume()
204 tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0); in gmc_v8_0_mc_resume()
205 WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp); in gmc_v8_0_mc_resume()
207 tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1); in gmc_v8_0_mc_resume()
208 tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1); in gmc_v8_0_mc_resume()
209 WREG32(mmBIF_FB_EN, tmp); in gmc_v8_0_mc_resume()
438 u32 tmp; in gmc_v8_0_mc_program() local
456 tmp = RREG32(mmVGA_HDP_CONTROL); in gmc_v8_0_mc_program()
457 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); in gmc_v8_0_mc_program()
458 WREG32(mmVGA_HDP_CONTROL, tmp); in gmc_v8_0_mc_program()
461 tmp = RREG32(mmVGA_RENDER_CONTROL); in gmc_v8_0_mc_program()
462 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); in gmc_v8_0_mc_program()
463 WREG32(mmVGA_RENDER_CONTROL, tmp); in gmc_v8_0_mc_program()
474 tmp = ((adev->gmc.vram_end >> 24) & 0xFFFF) << 16; in gmc_v8_0_mc_program()
475 tmp |= ((adev->gmc.vram_start >> 24) & 0xFFFF); in gmc_v8_0_mc_program()
476 WREG32(mmMC_VM_FB_LOCATION, tmp); in gmc_v8_0_mc_program()
492 tmp = RREG32(mmHDP_MISC_CNTL); in gmc_v8_0_mc_program()
493 tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 0); in gmc_v8_0_mc_program()
494 WREG32(mmHDP_MISC_CNTL, tmp); in gmc_v8_0_mc_program()
496 tmp = RREG32(mmHDP_HOST_PATH_CNTL); in gmc_v8_0_mc_program()
497 WREG32(mmHDP_HOST_PATH_CNTL, tmp); in gmc_v8_0_mc_program()
512 u32 tmp; in gmc_v8_0_mc_init() local
519 tmp = RREG32(mmMC_ARB_RAMCFG); in gmc_v8_0_mc_init()
520 if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)) { in gmc_v8_0_mc_init()
525 tmp = RREG32(mmMC_SHARED_CHMAP); in gmc_v8_0_mc_init()
526 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) { in gmc_v8_0_mc_init()
559 tmp = RREG32(mmCONFIG_MEMSIZE); in gmc_v8_0_mc_init()
561 if (tmp & 0xffff0000) { in gmc_v8_0_mc_init()
562 DRM_INFO("Probable bad vram size: 0x%08x\n", tmp); in gmc_v8_0_mc_init()
563 if (tmp & 0xffff) in gmc_v8_0_mc_init()
564 tmp &= 0xffff; in gmc_v8_0_mc_init()
566 adev->gmc.mc_vram_size = tmp * 1024ULL * 1024ULL; in gmc_v8_0_mc_init()
628 unsigned int tmp; in gmc_v8_0_flush_gpu_tlb_pasid() local
635 tmp = RREG32(mmATC_VMID0_PASID_MAPPING + vmid); in gmc_v8_0_flush_gpu_tlb_pasid()
636 if ((tmp & ATC_VMID0_PASID_MAPPING__VALID_MASK) && in gmc_v8_0_flush_gpu_tlb_pasid()
637 (tmp & ATC_VMID0_PASID_MAPPING__PASID_MASK) == pasid) { in gmc_v8_0_flush_gpu_tlb_pasid()
740 u32 tmp; in gmc_v8_0_set_fault_enable_default() local
742 tmp = RREG32(mmVM_CONTEXT1_CNTL); in gmc_v8_0_set_fault_enable_default()
743 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gmc_v8_0_set_fault_enable_default()
745 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gmc_v8_0_set_fault_enable_default()
747 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gmc_v8_0_set_fault_enable_default()
749 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gmc_v8_0_set_fault_enable_default()
751 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gmc_v8_0_set_fault_enable_default()
753 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gmc_v8_0_set_fault_enable_default()
755 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gmc_v8_0_set_fault_enable_default()
757 WREG32(mmVM_CONTEXT1_CNTL, tmp); in gmc_v8_0_set_fault_enable_default()
768 u32 tmp; in gmc_v8_0_set_prt() local
775 tmp = RREG32(mmVM_PRT_CNTL); in gmc_v8_0_set_prt()
776 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, in gmc_v8_0_set_prt()
778 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, in gmc_v8_0_set_prt()
780 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, in gmc_v8_0_set_prt()
782 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, in gmc_v8_0_set_prt()
784 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, in gmc_v8_0_set_prt()
786 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, in gmc_v8_0_set_prt()
788 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, in gmc_v8_0_set_prt()
790 WREG32(mmVM_PRT_CNTL, tmp); in gmc_v8_0_set_prt()
831 u32 tmp, field; in gmc_v8_0_gart_enable() local
842 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL); in gmc_v8_0_gart_enable()
843 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in gmc_v8_0_gart_enable()
844 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1); in gmc_v8_0_gart_enable()
845 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); in gmc_v8_0_gart_enable()
846 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1); in gmc_v8_0_gart_enable()
847 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0); in gmc_v8_0_gart_enable()
848 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp); in gmc_v8_0_gart_enable()
850 tmp = RREG32(mmVM_L2_CNTL); in gmc_v8_0_gart_enable()
851 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1); in gmc_v8_0_gart_enable()
852 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1); in gmc_v8_0_gart_enable()
853 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1); in gmc_v8_0_gart_enable()
854 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1); in gmc_v8_0_gart_enable()
855 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7); in gmc_v8_0_gart_enable()
856 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); in gmc_v8_0_gart_enable()
857 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1); in gmc_v8_0_gart_enable()
858 WREG32(mmVM_L2_CNTL, tmp); in gmc_v8_0_gart_enable()
859 tmp = RREG32(mmVM_L2_CNTL2); in gmc_v8_0_gart_enable()
860 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); in gmc_v8_0_gart_enable()
861 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); in gmc_v8_0_gart_enable()
862 WREG32(mmVM_L2_CNTL2, tmp); in gmc_v8_0_gart_enable()
865 tmp = RREG32(mmVM_L2_CNTL3); in gmc_v8_0_gart_enable()
866 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1); in gmc_v8_0_gart_enable()
867 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, field); in gmc_v8_0_gart_enable()
868 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, field); in gmc_v8_0_gart_enable()
869 WREG32(mmVM_L2_CNTL3, tmp); in gmc_v8_0_gart_enable()
871 tmp = RREG32(mmVM_L2_CNTL4); in gmc_v8_0_gart_enable()
872 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL, 0); in gmc_v8_0_gart_enable()
873 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED, 0); in gmc_v8_0_gart_enable()
874 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP, 0); in gmc_v8_0_gart_enable()
875 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL, 0); in gmc_v8_0_gart_enable()
876 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED, 0); in gmc_v8_0_gart_enable()
877 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP, 0); in gmc_v8_0_gart_enable()
878 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL, 0); in gmc_v8_0_gart_enable()
879 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED, 0); in gmc_v8_0_gart_enable()
880 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP, 0); in gmc_v8_0_gart_enable()
881 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL, 0); in gmc_v8_0_gart_enable()
882 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED, 0); in gmc_v8_0_gart_enable()
883 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP, 0); in gmc_v8_0_gart_enable()
884 WREG32(mmVM_L2_CNTL4, tmp); in gmc_v8_0_gart_enable()
892 tmp = RREG32(mmVM_CONTEXT0_CNTL); in gmc_v8_0_gart_enable()
893 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); in gmc_v8_0_gart_enable()
894 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); in gmc_v8_0_gart_enable()
895 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); in gmc_v8_0_gart_enable()
896 WREG32(mmVM_CONTEXT0_CNTL, tmp); in gmc_v8_0_gart_enable()
922 tmp = RREG32(mmVM_CONTEXT1_CNTL); in gmc_v8_0_gart_enable()
923 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); in gmc_v8_0_gart_enable()
924 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1); in gmc_v8_0_gart_enable()
925 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); in gmc_v8_0_gart_enable()
926 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); in gmc_v8_0_gart_enable()
927 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1); in gmc_v8_0_gart_enable()
928 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1); in gmc_v8_0_gart_enable()
929 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1); in gmc_v8_0_gart_enable()
930 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); in gmc_v8_0_gart_enable()
931 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); in gmc_v8_0_gart_enable()
932 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE, in gmc_v8_0_gart_enable()
934 WREG32(mmVM_CONTEXT1_CNTL, tmp); in gmc_v8_0_gart_enable()
973 u32 tmp; in gmc_v8_0_gart_disable() local
979 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL); in gmc_v8_0_gart_disable()
980 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); in gmc_v8_0_gart_disable()
981 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0); in gmc_v8_0_gart_disable()
982 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0); in gmc_v8_0_gart_disable()
983 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp); in gmc_v8_0_gart_disable()
985 tmp = RREG32(mmVM_L2_CNTL); in gmc_v8_0_gart_disable()
986 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0); in gmc_v8_0_gart_disable()
987 WREG32(mmVM_L2_CNTL, tmp); in gmc_v8_0_gart_disable()
1101 u32 tmp; in gmc_v8_0_sw_init() local
1105 tmp = RREG32(mmMC_SEQ_MISC0_FIJI); in gmc_v8_0_sw_init()
1107 tmp = RREG32(mmMC_SEQ_MISC0); in gmc_v8_0_sw_init()
1108 tmp &= MC_SEQ_MISC0__MT__MASK; in gmc_v8_0_sw_init()
1109 adev->gmc.vram_type = gmc_v8_0_convert_vram_type(tmp); in gmc_v8_0_sw_init()
1171 u64 tmp = RREG32(mmMC_VM_FB_OFFSET); in gmc_v8_0_sw_init() local
1173 tmp <<= 22; in gmc_v8_0_sw_init()
1174 adev->vm_manager.vram_base_offset = tmp; in gmc_v8_0_sw_init()
1273 u32 tmp = RREG32(mmSRBM_STATUS); in gmc_v8_0_is_idle() local
1275 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | in gmc_v8_0_is_idle()
1285 u32 tmp; in gmc_v8_0_wait_for_idle() local
1290 tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK | in gmc_v8_0_wait_for_idle()
1296 if (!tmp) in gmc_v8_0_wait_for_idle()
1308 u32 tmp = RREG32(mmSRBM_STATUS); in gmc_v8_0_check_soft_reset() local
1310 if (tmp & SRBM_STATUS__VMC_BUSY_MASK) in gmc_v8_0_check_soft_reset()
1314 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | in gmc_v8_0_check_soft_reset()
1354 u32 tmp; in gmc_v8_0_soft_reset() local
1356 tmp = RREG32(mmSRBM_SOFT_RESET); in gmc_v8_0_soft_reset()
1357 tmp |= srbm_soft_reset; in gmc_v8_0_soft_reset()
1358 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); in gmc_v8_0_soft_reset()
1359 WREG32(mmSRBM_SOFT_RESET, tmp); in gmc_v8_0_soft_reset()
1360 tmp = RREG32(mmSRBM_SOFT_RESET); in gmc_v8_0_soft_reset()
1364 tmp &= ~srbm_soft_reset; in gmc_v8_0_soft_reset()
1365 WREG32(mmSRBM_SOFT_RESET, tmp); in gmc_v8_0_soft_reset()
1366 tmp = RREG32(mmSRBM_SOFT_RESET); in gmc_v8_0_soft_reset()
1391 u32 tmp; in gmc_v8_0_vm_fault_interrupt_state() local
1403 tmp = RREG32(mmVM_CONTEXT0_CNTL); in gmc_v8_0_vm_fault_interrupt_state()
1404 tmp &= ~bits; in gmc_v8_0_vm_fault_interrupt_state()
1405 WREG32(mmVM_CONTEXT0_CNTL, tmp); in gmc_v8_0_vm_fault_interrupt_state()
1407 tmp = RREG32(mmVM_CONTEXT1_CNTL); in gmc_v8_0_vm_fault_interrupt_state()
1408 tmp &= ~bits; in gmc_v8_0_vm_fault_interrupt_state()
1409 WREG32(mmVM_CONTEXT1_CNTL, tmp); in gmc_v8_0_vm_fault_interrupt_state()
1413 tmp = RREG32(mmVM_CONTEXT0_CNTL); in gmc_v8_0_vm_fault_interrupt_state()
1414 tmp |= bits; in gmc_v8_0_vm_fault_interrupt_state()
1415 WREG32(mmVM_CONTEXT0_CNTL, tmp); in gmc_v8_0_vm_fault_interrupt_state()
1417 tmp = RREG32(mmVM_CONTEXT1_CNTL); in gmc_v8_0_vm_fault_interrupt_state()
1418 tmp |= bits; in gmc_v8_0_vm_fault_interrupt_state()
1419 WREG32(mmVM_CONTEXT1_CNTL, tmp); in gmc_v8_0_vm_fault_interrupt_state()