Lines Matching refs:umc
1284 adev->umc.funcs = &umc_v6_0_funcs; in gmc_v9_0_set_umc_funcs()
1287 adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM; in gmc_v9_0_set_umc_funcs()
1288 adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM; in gmc_v9_0_set_umc_funcs()
1289 adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM; in gmc_v9_0_set_umc_funcs()
1290 adev->umc.channel_offs = UMC_V6_1_PER_CHANNEL_OFFSET_VG20; in gmc_v9_0_set_umc_funcs()
1291 adev->umc.retire_unit = 1; in gmc_v9_0_set_umc_funcs()
1292 adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0]; in gmc_v9_0_set_umc_funcs()
1293 adev->umc.ras = &umc_v6_1_ras; in gmc_v9_0_set_umc_funcs()
1296 adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM; in gmc_v9_0_set_umc_funcs()
1297 adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM; in gmc_v9_0_set_umc_funcs()
1298 adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM; in gmc_v9_0_set_umc_funcs()
1299 adev->umc.channel_offs = UMC_V6_1_PER_CHANNEL_OFFSET_ARCT; in gmc_v9_0_set_umc_funcs()
1300 adev->umc.retire_unit = 1; in gmc_v9_0_set_umc_funcs()
1301 adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0]; in gmc_v9_0_set_umc_funcs()
1302 adev->umc.ras = &umc_v6_1_ras; in gmc_v9_0_set_umc_funcs()
1305 adev->umc.max_ras_err_cnt_per_query = in gmc_v9_0_set_umc_funcs()
1307 adev->umc.channel_inst_num = UMC_V6_7_CHANNEL_INSTANCE_NUM; in gmc_v9_0_set_umc_funcs()
1308 adev->umc.umc_inst_num = UMC_V6_7_UMC_INSTANCE_NUM; in gmc_v9_0_set_umc_funcs()
1309 adev->umc.channel_offs = UMC_V6_7_PER_CHANNEL_OFFSET; in gmc_v9_0_set_umc_funcs()
1310 adev->umc.retire_unit = (UMC_V6_7_NA_MAP_PA_NUM * 2); in gmc_v9_0_set_umc_funcs()
1312 adev->umc.ras = &umc_v6_7_ras; in gmc_v9_0_set_umc_funcs()
1314 adev->umc.channel_idx_tbl = &umc_v6_7_channel_idx_tbl_first[0][0]; in gmc_v9_0_set_umc_funcs()
1316 adev->umc.channel_idx_tbl = &umc_v6_7_channel_idx_tbl_second[0][0]; in gmc_v9_0_set_umc_funcs()
1322 if (adev->umc.ras) { in gmc_v9_0_set_umc_funcs()
1323 amdgpu_ras_register_ras_block(adev, &adev->umc.ras->ras_block); in gmc_v9_0_set_umc_funcs()
1325 strcpy(adev->umc.ras->ras_block.ras_comm.name, "umc"); in gmc_v9_0_set_umc_funcs()
1326 adev->umc.ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__UMC; in gmc_v9_0_set_umc_funcs()
1327 adev->umc.ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; in gmc_v9_0_set_umc_funcs()
1328 adev->umc.ras_if = &adev->umc.ras->ras_block.ras_comm; in gmc_v9_0_set_umc_funcs()
1331 if (!adev->umc.ras->ras_block.ras_late_init) in gmc_v9_0_set_umc_funcs()
1332 adev->umc.ras->ras_block.ras_late_init = amdgpu_umc_ras_late_init; in gmc_v9_0_set_umc_funcs()
1335 if (!adev->umc.ras->ras_block.ras_cb) in gmc_v9_0_set_umc_funcs()
1336 adev->umc.ras->ras_block.ras_cb = amdgpu_umc_process_ras_data_cb; in gmc_v9_0_set_umc_funcs()
1943 if (adev->umc.funcs && adev->umc.funcs->init_registers) in gmc_v9_0_hw_init()
1944 adev->umc.funcs->init_registers(adev); in gmc_v9_0_hw_init()