Lines Matching refs:HDP
56 WREG32_SOC15_NO_KIQ(HDP, 0, mmHDP_READ_CACHE_INVALIDATE, 1); in hdp_v4_0_invalidate_hdp()
59 HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1); in hdp_v4_0_invalidate_hdp()
74 err_data->ue_count += RREG32_SOC15(HDP, 0, mmHDP_EDC_CNT); in hdp_v4_0_query_ras_error_count()
83 WREG32_SOC15(HDP, 0, mmHDP_EDC_CNT, 0); in hdp_v4_0_reset_ras_error_count()
86 RREG32_SOC15(HDP, 0, mmHDP_EDC_CNT); in hdp_v4_0_reset_ras_error_count()
98 def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS)); in hdp_v4_0_update_clock_gating()
106 WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS), data); in hdp_v4_0_update_clock_gating()
108 def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL)); in hdp_v4_0_update_clock_gating()
122 WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL), data); in hdp_v4_0_update_clock_gating()
132 data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS)); in hdp_v4_0_get_clockgating_state()
141 WREG32_FIELD15(HDP, 0, HDP_MMHUB_CNTL, HDP_MMHUB_GCC, 1); in hdp_v4_0_init_registers()
147 WREG32_FIELD15(HDP, 0, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 1); in hdp_v4_0_init_registers()
150 WREG32_FIELD15(HDP, 0, HDP_MISC_CNTL, READ_BUFFER_WATERMARK, 2); in hdp_v4_0_init_registers()
152 WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE, (adev->gmc.vram_start >> 8)); in hdp_v4_0_init_registers()
153 WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE_HI, (adev->gmc.vram_start >> 40)); in hdp_v4_0_init_registers()