Lines Matching refs:gfx
53 err = amdgpu_ucode_request(adev, &adev->gfx.imu_fw, fw_name); in imu_v11_0_init_microcode()
56 imu_hdr = (const struct imu_firmware_header_v1_0 *)adev->gfx.imu_fw->data; in imu_v11_0_init_microcode()
57 adev->gfx.imu_fw_version = le32_to_cpu(imu_hdr->header.ucode_version); in imu_v11_0_init_microcode()
63 info->fw = adev->gfx.imu_fw; in imu_v11_0_init_microcode()
68 info->fw = adev->gfx.imu_fw; in imu_v11_0_init_microcode()
78 amdgpu_ucode_release(&adev->gfx.imu_fw); in imu_v11_0_init_microcode()
90 if (!adev->gfx.imu_fw) in imu_v11_0_load_microcode()
93 hdr = (const struct imu_firmware_header_v1_0 *)adev->gfx.imu_fw->data; in imu_v11_0_load_microcode()
96 fw_data = (const __le32 *)(adev->gfx.imu_fw->data + in imu_v11_0_load_microcode()
105 WREG32_SOC15(GC, 0, regGFX_IMU_I_RAM_ADDR, adev->gfx.imu_fw_version); in imu_v11_0_load_microcode()
107 fw_data = (const __le32 *)(adev->gfx.imu_fw->data + in imu_v11_0_load_microcode()
117 WREG32_SOC15(GC, 0, regGFX_IMU_D_RAM_ADDR, adev->gfx.imu_fw_version); in imu_v11_0_load_microcode()
149 if (adev->gfx.imu.mode == DEBUG_MODE) { in imu_v11_0_setup()