Lines Matching refs:mqd
631 struct v10_compute_mqd *mqd = ring->mqd_ptr; in mes_v10_1_mqd_init() local
635 mqd->header = 0xC0310800; in mes_v10_1_mqd_init()
636 mqd->compute_pipelinestat_enable = 0x00000001; in mes_v10_1_mqd_init()
637 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; in mes_v10_1_mqd_init()
638 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; in mes_v10_1_mqd_init()
639 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; in mes_v10_1_mqd_init()
640 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; in mes_v10_1_mqd_init()
641 mqd->compute_misc_reserved = 0x00000003; in mes_v10_1_mqd_init()
650 mqd->cp_hqd_eop_base_addr_lo = lower_32_bits(eop_base_addr); in mes_v10_1_mqd_init()
651 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); in mes_v10_1_mqd_init()
652 mqd->cp_hqd_eop_control = tmp; in mes_v10_1_mqd_init()
656 mqd->cp_hqd_pq_rptr = 0; in mes_v10_1_mqd_init()
657 mqd->cp_hqd_pq_wptr_lo = 0; in mes_v10_1_mqd_init()
658 mqd->cp_hqd_pq_wptr_hi = 0; in mes_v10_1_mqd_init()
661 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; in mes_v10_1_mqd_init()
662 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); in mes_v10_1_mqd_init()
667 mqd->cp_mqd_control = tmp; in mes_v10_1_mqd_init()
671 mqd->cp_hqd_pq_base_lo = lower_32_bits(hqd_gpu_addr); in mes_v10_1_mqd_init()
672 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); in mes_v10_1_mqd_init()
676 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; in mes_v10_1_mqd_init()
677 mqd->cp_hqd_pq_rptr_report_addr_hi = in mes_v10_1_mqd_init()
682 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffff8; in mes_v10_1_mqd_init()
683 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; in mes_v10_1_mqd_init()
699 mqd->cp_hqd_pq_control = tmp; in mes_v10_1_mqd_init()
716 mqd->cp_hqd_pq_doorbell_control = tmp; in mes_v10_1_mqd_init()
718 mqd->cp_hqd_vmid = 0; in mes_v10_1_mqd_init()
720 mqd->cp_hqd_active = 1; in mes_v10_1_mqd_init()
721 mqd->cp_hqd_persistent_state = mmCP_HQD_PERSISTENT_STATE_DEFAULT; in mes_v10_1_mqd_init()
722 mqd->cp_hqd_ib_control = mmCP_HQD_IB_CONTROL_DEFAULT; in mes_v10_1_mqd_init()
723 mqd->cp_hqd_iq_timer = mmCP_HQD_IQ_TIMER_DEFAULT; in mes_v10_1_mqd_init()
724 mqd->cp_hqd_quantum = mmCP_HQD_QUANTUM_DEFAULT; in mes_v10_1_mqd_init()
729 mqd->cp_hqd_suspend_cntl_stack_offset = tmp; in mes_v10_1_mqd_init()
737 struct v10_compute_mqd *mqd = ring->mqd_ptr;
756 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo);
757 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi);
765 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo);
766 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi);
770 mqd->cp_hqd_pq_rptr_report_addr_lo);
772 mqd->cp_hqd_pq_rptr_report_addr_hi);
775 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL, mqd->cp_hqd_pq_control);
779 mqd->cp_hqd_pq_wptr_poll_addr_lo);
781 mqd->cp_hqd_pq_wptr_poll_addr_hi);
785 mqd->cp_hqd_pq_doorbell_control);
788 WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE, mqd->cp_hqd_persistent_state);
791 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, mqd->cp_hqd_active);