Lines Matching refs:adev
215 static int nv_query_video_codecs(struct amdgpu_device *adev, bool encode, in nv_query_video_codecs() argument
218 if (adev->vcn.num_vcn_inst == hweight8(adev->vcn.harvest_config)) in nv_query_video_codecs()
221 switch (adev->ip_versions[UVD_HWIP][0]) { in nv_query_video_codecs()
225 if (amdgpu_sriov_vf(adev)) { in nv_query_video_codecs()
226 if (adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) { in nv_query_video_codecs()
238 if (adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) { in nv_query_video_codecs()
286 static u32 nv_pcie_rreg(struct amdgpu_device *adev, u32 reg) in nv_pcie_rreg() argument
289 address = adev->nbio.funcs->get_pcie_index_offset(adev); in nv_pcie_rreg()
290 data = adev->nbio.funcs->get_pcie_data_offset(adev); in nv_pcie_rreg()
292 return amdgpu_device_indirect_rreg(adev, address, data, reg); in nv_pcie_rreg()
295 static void nv_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) in nv_pcie_wreg() argument
299 address = adev->nbio.funcs->get_pcie_index_offset(adev); in nv_pcie_wreg()
300 data = adev->nbio.funcs->get_pcie_data_offset(adev); in nv_pcie_wreg()
302 amdgpu_device_indirect_wreg(adev, address, data, reg, v); in nv_pcie_wreg()
305 static u64 nv_pcie_rreg64(struct amdgpu_device *adev, u32 reg) in nv_pcie_rreg64() argument
308 address = adev->nbio.funcs->get_pcie_index_offset(adev); in nv_pcie_rreg64()
309 data = adev->nbio.funcs->get_pcie_data_offset(adev); in nv_pcie_rreg64()
311 return amdgpu_device_indirect_rreg64(adev, address, data, reg); in nv_pcie_rreg64()
314 static void nv_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v) in nv_pcie_wreg64() argument
318 address = adev->nbio.funcs->get_pcie_index_offset(adev); in nv_pcie_wreg64()
319 data = adev->nbio.funcs->get_pcie_data_offset(adev); in nv_pcie_wreg64()
321 amdgpu_device_indirect_wreg64(adev, address, data, reg, v); in nv_pcie_wreg64()
324 static u32 nv_didt_rreg(struct amdgpu_device *adev, u32 reg) in nv_didt_rreg() argument
332 spin_lock_irqsave(&adev->didt_idx_lock, flags); in nv_didt_rreg()
335 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); in nv_didt_rreg()
339 static void nv_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) in nv_didt_wreg() argument
346 spin_lock_irqsave(&adev->didt_idx_lock, flags); in nv_didt_wreg()
349 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); in nv_didt_wreg()
352 static u32 nv_get_config_memsize(struct amdgpu_device *adev) in nv_get_config_memsize() argument
354 return adev->nbio.funcs->get_memsize(adev); in nv_get_config_memsize()
357 static u32 nv_get_xclk(struct amdgpu_device *adev) in nv_get_xclk() argument
359 return adev->clock.spll.reference_freq; in nv_get_xclk()
363 void nv_grbm_select(struct amdgpu_device *adev, in nv_grbm_select() argument
375 static void nv_vga_set_state(struct amdgpu_device *adev, bool state) in nv_vga_set_state() argument
380 static bool nv_read_disabled_bios(struct amdgpu_device *adev) in nv_read_disabled_bios() argument
408 static uint32_t nv_read_indexed_register(struct amdgpu_device *adev, u32 se_num, in nv_read_indexed_register() argument
413 mutex_lock(&adev->grbm_idx_mutex); in nv_read_indexed_register()
415 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); in nv_read_indexed_register()
420 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); in nv_read_indexed_register()
421 mutex_unlock(&adev->grbm_idx_mutex); in nv_read_indexed_register()
425 static uint32_t nv_get_register_value(struct amdgpu_device *adev, in nv_get_register_value() argument
430 return nv_read_indexed_register(adev, se_num, sh_num, reg_offset); in nv_get_register_value()
433 return adev->gfx.config.gb_addr_config; in nv_get_register_value()
438 static int nv_read_register(struct amdgpu_device *adev, u32 se_num, in nv_read_register() argument
447 if (!adev->reg_offset[en->hwip][en->inst]) in nv_read_register()
449 else if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg] in nv_read_register()
453 *value = nv_get_register_value(adev, in nv_read_register()
461 static int nv_asic_mode2_reset(struct amdgpu_device *adev) in nv_asic_mode2_reset() argument
466 amdgpu_atombios_scratch_regs_engine_hung(adev, true); in nv_asic_mode2_reset()
469 pci_clear_master(adev->pdev); in nv_asic_mode2_reset()
471 amdgpu_device_cache_pci_state(adev->pdev); in nv_asic_mode2_reset()
473 ret = amdgpu_dpm_mode2_reset(adev); in nv_asic_mode2_reset()
475 dev_err(adev->dev, "GPU mode2 reset failed\n"); in nv_asic_mode2_reset()
477 amdgpu_device_load_pci_state(adev->pdev); in nv_asic_mode2_reset()
480 for (i = 0; i < adev->usec_timeout; i++) { in nv_asic_mode2_reset()
481 u32 memsize = adev->nbio.funcs->get_memsize(adev); in nv_asic_mode2_reset()
488 amdgpu_atombios_scratch_regs_engine_hung(adev, false); in nv_asic_mode2_reset()
494 nv_asic_reset_method(struct amdgpu_device *adev) in nv_asic_reset_method() argument
503 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n", in nv_asic_reset_method()
506 switch (adev->ip_versions[MP1_HWIP][0]) { in nv_asic_reset_method()
519 if (amdgpu_dpm_is_baco_supported(adev)) in nv_asic_reset_method()
526 static int nv_asic_reset(struct amdgpu_device *adev) in nv_asic_reset() argument
530 switch (nv_asic_reset_method(adev)) { in nv_asic_reset()
532 dev_info(adev->dev, "PCI reset\n"); in nv_asic_reset()
533 ret = amdgpu_device_pci_reset(adev); in nv_asic_reset()
536 dev_info(adev->dev, "BACO reset\n"); in nv_asic_reset()
537 ret = amdgpu_dpm_baco_reset(adev); in nv_asic_reset()
540 dev_info(adev->dev, "MODE2 reset\n"); in nv_asic_reset()
541 ret = nv_asic_mode2_reset(adev); in nv_asic_reset()
544 dev_info(adev->dev, "MODE1 reset\n"); in nv_asic_reset()
545 ret = amdgpu_device_mode1_reset(adev); in nv_asic_reset()
552 static int nv_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) in nv_set_uvd_clocks() argument
558 static int nv_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) in nv_set_vce_clocks() argument
564 static void nv_pcie_gen3_enable(struct amdgpu_device *adev) in nv_pcie_gen3_enable() argument
566 if (pci_is_root_bus(adev->pdev->bus)) in nv_pcie_gen3_enable()
572 if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | in nv_pcie_gen3_enable()
579 static void nv_program_aspm(struct amdgpu_device *adev) in nv_program_aspm() argument
581 if (!amdgpu_device_should_use_aspm(adev)) in nv_program_aspm()
584 if (!(adev->flags & AMD_IS_APU) && in nv_program_aspm()
585 (adev->nbio.funcs->program_aspm)) in nv_program_aspm()
586 adev->nbio.funcs->program_aspm(adev); in nv_program_aspm()
590 static void nv_enable_doorbell_aperture(struct amdgpu_device *adev, in nv_enable_doorbell_aperture() argument
593 adev->nbio.funcs->enable_doorbell_aperture(adev, enable); in nv_enable_doorbell_aperture()
594 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable); in nv_enable_doorbell_aperture()
606 void nv_set_virt_ops(struct amdgpu_device *adev) in nv_set_virt_ops() argument
608 adev->virt.ops = &xgpu_nv_virt_ops; in nv_set_virt_ops()
611 static uint32_t nv_get_rev_id(struct amdgpu_device *adev) in nv_get_rev_id() argument
613 return adev->nbio.funcs->get_rev_id(adev); in nv_get_rev_id()
616 static bool nv_need_full_reset(struct amdgpu_device *adev) in nv_need_full_reset() argument
621 static bool nv_need_reset_on_init(struct amdgpu_device *adev) in nv_need_reset_on_init() argument
625 if (adev->flags & AMD_IS_APU) in nv_need_reset_on_init()
638 static uint64_t nv_get_pcie_replay_count(struct amdgpu_device *adev) in nv_get_pcie_replay_count() argument
648 static void nv_init_doorbell_index(struct amdgpu_device *adev) in nv_init_doorbell_index() argument
650 adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ; in nv_init_doorbell_index()
651 adev->doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0; in nv_init_doorbell_index()
652 adev->doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1; in nv_init_doorbell_index()
653 adev->doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2; in nv_init_doorbell_index()
654 adev->doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3; in nv_init_doorbell_index()
655 adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4; in nv_init_doorbell_index()
656 adev->doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5; in nv_init_doorbell_index()
657 adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6; in nv_init_doorbell_index()
658 adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7; in nv_init_doorbell_index()
659 adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START; in nv_init_doorbell_index()
660 adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END; in nv_init_doorbell_index()
661 adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0; in nv_init_doorbell_index()
662 adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1; in nv_init_doorbell_index()
663 adev->doorbell_index.gfx_userqueue_start = in nv_init_doorbell_index()
665 adev->doorbell_index.gfx_userqueue_end = in nv_init_doorbell_index()
667 adev->doorbell_index.mes_ring0 = AMDGPU_NAVI10_DOORBELL_MES_RING0; in nv_init_doorbell_index()
668 adev->doorbell_index.mes_ring1 = AMDGPU_NAVI10_DOORBELL_MES_RING1; in nv_init_doorbell_index()
669 adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0; in nv_init_doorbell_index()
670 adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1; in nv_init_doorbell_index()
671 adev->doorbell_index.sdma_engine[2] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE2; in nv_init_doorbell_index()
672 adev->doorbell_index.sdma_engine[3] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE3; in nv_init_doorbell_index()
673 adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH; in nv_init_doorbell_index()
674 adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1; in nv_init_doorbell_index()
675 adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3; in nv_init_doorbell_index()
676 adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5; in nv_init_doorbell_index()
677 adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7; in nv_init_doorbell_index()
678 adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP; in nv_init_doorbell_index()
679 adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP; in nv_init_doorbell_index()
681 adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT << 1; in nv_init_doorbell_index()
682 adev->doorbell_index.sdma_doorbell_range = 20; in nv_init_doorbell_index()
685 static void nv_pre_asic_init(struct amdgpu_device *adev) in nv_pre_asic_init() argument
689 static int nv_update_umd_stable_pstate(struct amdgpu_device *adev, in nv_update_umd_stable_pstate() argument
693 amdgpu_gfx_rlc_enter_safe_mode(adev); in nv_update_umd_stable_pstate()
695 amdgpu_gfx_rlc_exit_safe_mode(adev); in nv_update_umd_stable_pstate()
697 if (adev->gfx.funcs->update_perfmon_mgcg) in nv_update_umd_stable_pstate()
698 adev->gfx.funcs->update_perfmon_mgcg(adev, !enter); in nv_update_umd_stable_pstate()
700 if (!(adev->flags & AMD_IS_APU) && in nv_update_umd_stable_pstate()
701 (adev->nbio.funcs->enable_aspm) && in nv_update_umd_stable_pstate()
702 amdgpu_device_should_use_aspm(adev)) in nv_update_umd_stable_pstate()
703 adev->nbio.funcs->enable_aspm(adev, !enter); in nv_update_umd_stable_pstate()
733 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in nv_common_early_init() local
735 if (!amdgpu_sriov_vf(adev)) { in nv_common_early_init()
736 adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET; in nv_common_early_init()
737 adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET; in nv_common_early_init()
739 adev->smc_rreg = NULL; in nv_common_early_init()
740 adev->smc_wreg = NULL; in nv_common_early_init()
741 adev->pcie_rreg = &nv_pcie_rreg; in nv_common_early_init()
742 adev->pcie_wreg = &nv_pcie_wreg; in nv_common_early_init()
743 adev->pcie_rreg64 = &nv_pcie_rreg64; in nv_common_early_init()
744 adev->pcie_wreg64 = &nv_pcie_wreg64; in nv_common_early_init()
745 adev->pciep_rreg = amdgpu_device_pcie_port_rreg; in nv_common_early_init()
746 adev->pciep_wreg = amdgpu_device_pcie_port_wreg; in nv_common_early_init()
749 adev->uvd_ctx_rreg = NULL; in nv_common_early_init()
750 adev->uvd_ctx_wreg = NULL; in nv_common_early_init()
752 adev->didt_rreg = &nv_didt_rreg; in nv_common_early_init()
753 adev->didt_wreg = &nv_didt_wreg; in nv_common_early_init()
755 adev->asic_funcs = &nv_asic_funcs; in nv_common_early_init()
757 adev->rev_id = nv_get_rev_id(adev); in nv_common_early_init()
758 adev->external_rev_id = 0xff; in nv_common_early_init()
762 switch (adev->ip_versions[GC_HWIP][0]) { in nv_common_early_init()
764 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in nv_common_early_init()
779 adev->pg_flags = AMD_PG_SUPPORT_VCN | in nv_common_early_init()
783 adev->external_rev_id = adev->rev_id + 0x1; in nv_common_early_init()
786 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in nv_common_early_init()
801 adev->pg_flags = AMD_PG_SUPPORT_VCN | in nv_common_early_init()
804 adev->external_rev_id = adev->rev_id + 20; in nv_common_early_init()
807 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in nv_common_early_init()
823 adev->pg_flags = AMD_PG_SUPPORT_VCN | in nv_common_early_init()
831 if (amdgpu_sriov_vf(adev)) in nv_common_early_init()
832 adev->rev_id = 0; in nv_common_early_init()
833 adev->external_rev_id = adev->rev_id + 0xa; in nv_common_early_init()
836 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in nv_common_early_init()
847 adev->pg_flags = AMD_PG_SUPPORT_VCN | in nv_common_early_init()
852 if (amdgpu_sriov_vf(adev)) { in nv_common_early_init()
854 adev->cg_flags = 0; in nv_common_early_init()
855 adev->pg_flags = 0; in nv_common_early_init()
857 adev->external_rev_id = adev->rev_id + 0x28; in nv_common_early_init()
860 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in nv_common_early_init()
871 adev->pg_flags = AMD_PG_SUPPORT_VCN | in nv_common_early_init()
876 adev->external_rev_id = adev->rev_id + 0x32; in nv_common_early_init()
879 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in nv_common_early_init()
894 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG | in nv_common_early_init()
898 if (adev->apu_flags & AMD_APU_IS_VANGOGH) in nv_common_early_init()
899 adev->external_rev_id = adev->rev_id + 0x01; in nv_common_early_init()
902 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in nv_common_early_init()
913 adev->pg_flags = AMD_PG_SUPPORT_VCN | in nv_common_early_init()
918 adev->external_rev_id = adev->rev_id + 0x3c; in nv_common_early_init()
921 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in nv_common_early_init()
931 adev->pg_flags = AMD_PG_SUPPORT_VCN | in nv_common_early_init()
935 adev->external_rev_id = adev->rev_id + 0x46; in nv_common_early_init()
938 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in nv_common_early_init()
957 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG | in nv_common_early_init()
961 if (adev->pdev->device == 0x1681) in nv_common_early_init()
962 adev->external_rev_id = 0x20; in nv_common_early_init()
964 adev->external_rev_id = adev->rev_id + 0x01; in nv_common_early_init()
968 adev->cg_flags = 0; in nv_common_early_init()
969 adev->pg_flags = 0; in nv_common_early_init()
970 adev->external_rev_id = adev->rev_id + 0x82; in nv_common_early_init()
973 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in nv_common_early_init()
992 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG | in nv_common_early_init()
996 adev->external_rev_id = adev->rev_id + 0x01; in nv_common_early_init()
999 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in nv_common_early_init()
1018 adev->pg_flags = AMD_PG_SUPPORT_VCN | in nv_common_early_init()
1022 adev->external_rev_id = adev->rev_id + 0x01; in nv_common_early_init()
1029 if (adev->harvest_ip_mask & AMD_HARVEST_IP_VCN_MASK) in nv_common_early_init()
1030 adev->pg_flags &= ~(AMD_PG_SUPPORT_VCN | in nv_common_early_init()
1034 if (amdgpu_sriov_vf(adev)) { in nv_common_early_init()
1035 amdgpu_virt_init_setting(adev); in nv_common_early_init()
1036 xgpu_nv_mailbox_set_irq_funcs(adev); in nv_common_early_init()
1044 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in nv_common_late_init() local
1046 if (amdgpu_sriov_vf(adev)) { in nv_common_late_init()
1047 xgpu_nv_mailbox_get_irq(adev); in nv_common_late_init()
1048 if (adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) { in nv_common_late_init()
1049 amdgpu_virt_update_sriov_video_codec(adev, in nv_common_late_init()
1055 amdgpu_virt_update_sriov_video_codec(adev, in nv_common_late_init()
1068 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in nv_common_sw_init() local
1070 if (amdgpu_sriov_vf(adev)) in nv_common_sw_init()
1071 xgpu_nv_mailbox_add_irq_id(adev); in nv_common_sw_init()
1083 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in nv_common_hw_init() local
1085 if (adev->nbio.funcs->apply_lc_spc_mode_wa) in nv_common_hw_init()
1086 adev->nbio.funcs->apply_lc_spc_mode_wa(adev); in nv_common_hw_init()
1088 if (adev->nbio.funcs->apply_l1_link_width_reconfig_wa) in nv_common_hw_init()
1089 adev->nbio.funcs->apply_l1_link_width_reconfig_wa(adev); in nv_common_hw_init()
1092 nv_pcie_gen3_enable(adev); in nv_common_hw_init()
1094 nv_program_aspm(adev); in nv_common_hw_init()
1096 adev->nbio.funcs->init_registers(adev); in nv_common_hw_init()
1101 if (adev->nbio.funcs->remap_hdp_registers && !amdgpu_sriov_vf(adev)) in nv_common_hw_init()
1102 adev->nbio.funcs->remap_hdp_registers(adev); in nv_common_hw_init()
1104 nv_enable_doorbell_aperture(adev, true); in nv_common_hw_init()
1111 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in nv_common_hw_fini() local
1114 nv_enable_doorbell_aperture(adev, false); in nv_common_hw_fini()
1121 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in nv_common_suspend() local
1123 return nv_common_hw_fini(adev); in nv_common_suspend()
1128 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in nv_common_resume() local
1130 return nv_common_hw_init(adev); in nv_common_resume()
1151 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in nv_common_set_clockgating_state() local
1153 if (amdgpu_sriov_vf(adev)) in nv_common_set_clockgating_state()
1156 switch (adev->ip_versions[NBIO_HWIP][0]) { in nv_common_set_clockgating_state()
1164 adev->nbio.funcs->update_medium_grain_clock_gating(adev, in nv_common_set_clockgating_state()
1166 adev->nbio.funcs->update_medium_grain_light_sleep(adev, in nv_common_set_clockgating_state()
1168 adev->hdp.funcs->update_clock_gating(adev, in nv_common_set_clockgating_state()
1170 adev->smuio.funcs->update_rom_clock_gating(adev, in nv_common_set_clockgating_state()
1188 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in nv_common_get_clockgating_state() local
1190 if (amdgpu_sriov_vf(adev)) in nv_common_get_clockgating_state()
1193 adev->nbio.funcs->get_clockgating_state(adev, flags); in nv_common_get_clockgating_state()
1195 adev->hdp.funcs->get_clock_gating_state(adev, flags); in nv_common_get_clockgating_state()
1197 adev->smuio.funcs->get_clock_gating_state(adev, flags); in nv_common_get_clockgating_state()