Lines Matching refs:sdma
117 for (i = 0; i < adev->sdma.num_instances; i++) in sdma_v2_4_free_microcode()
118 amdgpu_ucode_release(&adev->sdma.instance[i].fw); in sdma_v2_4_free_microcode()
148 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v2_4_init_microcode()
153 err = amdgpu_ucode_request(adev, &adev->sdma.instance[i].fw, fw_name); in sdma_v2_4_init_microcode()
156 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; in sdma_v2_4_init_microcode()
157 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version); in sdma_v2_4_init_microcode()
158 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version); in sdma_v2_4_init_microcode()
159 if (adev->sdma.instance[i].feature_version >= 20) in sdma_v2_4_init_microcode()
160 adev->sdma.instance[i].burst_nop = true; in sdma_v2_4_init_microcode()
165 info->fw = adev->sdma.instance[i].fw; in sdma_v2_4_init_microcode()
175 for (i = 0; i < adev->sdma.num_instances; i++) in sdma_v2_4_init_microcode()
176 amdgpu_ucode_release(&adev->sdma.instance[i].fw); in sdma_v2_4_init_microcode()
225 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); in sdma_v2_4_ring_insert_nop() local
229 if (sdma && sdma->burst_nop && (i == 0)) in sdma_v2_4_ring_insert_nop()
344 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v2_4_gfx_stop()
384 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v2_4_enable()
409 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v2_4_gfx_resume()
410 ring = &adev->sdma.instance[i].ring; in sdma_v2_4_gfx_resume()
474 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v2_4_gfx_resume()
475 ring = &adev->sdma.instance[i].ring; in sdma_v2_4_gfx_resume()
742 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); in sdma_v2_4_ring_pad_ib() local
748 if (sdma && sdma->burst_nop && (i == 0)) in sdma_v2_4_ring_pad_ib()
822 adev->sdma.num_instances = SDMA_MAX_INSTANCE; in sdma_v2_4_early_init()
840 &adev->sdma.trap_irq); in sdma_v2_4_sw_init()
846 &adev->sdma.illegal_inst_irq); in sdma_v2_4_sw_init()
852 &adev->sdma.illegal_inst_irq); in sdma_v2_4_sw_init()
862 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v2_4_sw_init()
863 ring = &adev->sdma.instance[i].ring; in sdma_v2_4_sw_init()
867 r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq, in sdma_v2_4_sw_init()
883 for (i = 0; i < adev->sdma.num_instances; i++) in sdma_v2_4_sw_fini()
884 amdgpu_ring_fini(&adev->sdma.instance[i].ring); in sdma_v2_4_sw_fini()
1056 amdgpu_fence_process(&adev->sdma.instance[0].ring); in sdma_v2_4_process_trap_irq()
1069 amdgpu_fence_process(&adev->sdma.instance[1].ring); in sdma_v2_4_process_trap_irq()
1094 drm_sched_fault(&adev->sdma.instance[instance_id].ring.sched); in sdma_v2_4_process_illegal_inst_irq()
1160 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v2_4_set_ring_funcs()
1161 adev->sdma.instance[i].ring.funcs = &sdma_v2_4_ring_funcs; in sdma_v2_4_set_ring_funcs()
1162 adev->sdma.instance[i].ring.me = i; in sdma_v2_4_set_ring_funcs()
1177 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST; in sdma_v2_4_set_irq_funcs()
1178 adev->sdma.trap_irq.funcs = &sdma_v2_4_trap_irq_funcs; in sdma_v2_4_set_irq_funcs()
1179 adev->sdma.illegal_inst_irq.funcs = &sdma_v2_4_illegal_inst_irq_funcs; in sdma_v2_4_set_irq_funcs()
1246 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; in sdma_v2_4_set_buffer_funcs()
1262 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v2_4_set_vm_pte_funcs()
1264 &adev->sdma.instance[i].ring.sched; in sdma_v2_4_set_vm_pte_funcs()
1266 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; in sdma_v2_4_set_vm_pte_funcs()