Lines Matching refs:ib
231 struct amdgpu_ib *ib, in sdma_v5_2_ring_emit_ib() argument
250 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); in sdma_v5_2_ring_emit_ib()
251 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in sdma_v5_2_ring_emit_ib()
252 amdgpu_ring_write(ring, ib->length_dw); in sdma_v5_2_ring_emit_ib()
905 struct amdgpu_ib ib; in sdma_v5_2_ring_test_ib() local
914 memset(&ib, 0, sizeof(ib)); in sdma_v5_2_ring_test_ib()
919 ib.gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); in sdma_v5_2_ring_test_ib()
920 ib.ptr = (void *)amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); in sdma_v5_2_ring_test_ib()
937 r = amdgpu_ib_get(adev, NULL, 256, AMDGPU_IB_POOL_DIRECT, &ib); in sdma_v5_2_ring_test_ib()
944 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | in sdma_v5_2_ring_test_ib()
946 ib.ptr[1] = lower_32_bits(gpu_addr); in sdma_v5_2_ring_test_ib()
947 ib.ptr[2] = upper_32_bits(gpu_addr); in sdma_v5_2_ring_test_ib()
948 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0); in sdma_v5_2_ring_test_ib()
949 ib.ptr[4] = 0xDEADBEEF; in sdma_v5_2_ring_test_ib()
950 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); in sdma_v5_2_ring_test_ib()
951 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); in sdma_v5_2_ring_test_ib()
952 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); in sdma_v5_2_ring_test_ib()
953 ib.length_dw = 8; in sdma_v5_2_ring_test_ib()
955 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); in sdma_v5_2_ring_test_ib()
980 amdgpu_ib_free(adev, &ib, NULL); in sdma_v5_2_ring_test_ib()
999 static void sdma_v5_2_vm_copy_pte(struct amdgpu_ib *ib, in sdma_v5_2_vm_copy_pte() argument
1005 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | in sdma_v5_2_vm_copy_pte()
1007 ib->ptr[ib->length_dw++] = bytes - 1; in sdma_v5_2_vm_copy_pte()
1008 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ in sdma_v5_2_vm_copy_pte()
1009 ib->ptr[ib->length_dw++] = lower_32_bits(src); in sdma_v5_2_vm_copy_pte()
1010 ib->ptr[ib->length_dw++] = upper_32_bits(src); in sdma_v5_2_vm_copy_pte()
1011 ib->ptr[ib->length_dw++] = lower_32_bits(pe); in sdma_v5_2_vm_copy_pte()
1012 ib->ptr[ib->length_dw++] = upper_32_bits(pe); in sdma_v5_2_vm_copy_pte()
1027 static void sdma_v5_2_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, in sdma_v5_2_vm_write_pte() argument
1033 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | in sdma_v5_2_vm_write_pte()
1035 ib->ptr[ib->length_dw++] = lower_32_bits(pe); in sdma_v5_2_vm_write_pte()
1036 ib->ptr[ib->length_dw++] = upper_32_bits(pe); in sdma_v5_2_vm_write_pte()
1037 ib->ptr[ib->length_dw++] = ndw - 1; in sdma_v5_2_vm_write_pte()
1039 ib->ptr[ib->length_dw++] = lower_32_bits(value); in sdma_v5_2_vm_write_pte()
1040 ib->ptr[ib->length_dw++] = upper_32_bits(value); in sdma_v5_2_vm_write_pte()
1057 static void sdma_v5_2_vm_set_pte_pde(struct amdgpu_ib *ib, in sdma_v5_2_vm_set_pte_pde() argument
1063 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE); in sdma_v5_2_vm_set_pte_pde()
1064 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ in sdma_v5_2_vm_set_pte_pde()
1065 ib->ptr[ib->length_dw++] = upper_32_bits(pe); in sdma_v5_2_vm_set_pte_pde()
1066 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ in sdma_v5_2_vm_set_pte_pde()
1067 ib->ptr[ib->length_dw++] = upper_32_bits(flags); in sdma_v5_2_vm_set_pte_pde()
1068 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ in sdma_v5_2_vm_set_pte_pde()
1069 ib->ptr[ib->length_dw++] = upper_32_bits(addr); in sdma_v5_2_vm_set_pte_pde()
1070 ib->ptr[ib->length_dw++] = incr; /* increment size */ in sdma_v5_2_vm_set_pte_pde()
1071 ib->ptr[ib->length_dw++] = 0; in sdma_v5_2_vm_set_pte_pde()
1072 ib->ptr[ib->length_dw++] = count - 1; /* number of entries */ in sdma_v5_2_vm_set_pte_pde()
1083 static void sdma_v5_2_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) in sdma_v5_2_ring_pad_ib() argument
1089 pad_count = (-ib->length_dw) & 0x7; in sdma_v5_2_ring_pad_ib()
1092 ib->ptr[ib->length_dw++] = in sdma_v5_2_ring_pad_ib()
1096 ib->ptr[ib->length_dw++] = in sdma_v5_2_ring_pad_ib()
1728 static void sdma_v5_2_emit_copy_buffer(struct amdgpu_ib *ib, in sdma_v5_2_emit_copy_buffer() argument
1734 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | in sdma_v5_2_emit_copy_buffer()
1737 ib->ptr[ib->length_dw++] = byte_count - 1; in sdma_v5_2_emit_copy_buffer()
1738 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ in sdma_v5_2_emit_copy_buffer()
1739 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); in sdma_v5_2_emit_copy_buffer()
1740 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); in sdma_v5_2_emit_copy_buffer()
1741 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); in sdma_v5_2_emit_copy_buffer()
1742 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); in sdma_v5_2_emit_copy_buffer()
1755 static void sdma_v5_2_emit_fill_buffer(struct amdgpu_ib *ib, in sdma_v5_2_emit_fill_buffer() argument
1760 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL); in sdma_v5_2_emit_fill_buffer()
1761 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); in sdma_v5_2_emit_fill_buffer()
1762 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); in sdma_v5_2_emit_fill_buffer()
1763 ib->ptr[ib->length_dw++] = src_data; in sdma_v5_2_emit_fill_buffer()
1764 ib->ptr[ib->length_dw++] = byte_count - 1; in sdma_v5_2_emit_fill_buffer()