Lines Matching refs:WREG32_SMC_P
1871 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~UPLL_CTLREQ_MASK); in si_vce_send_vcepll_ctlreq()
1876 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, UPLL_CTLREQ_MASK, ~UPLL_CTLREQ_MASK); in si_vce_send_vcepll_ctlreq()
1888 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~UPLL_CTLREQ_MASK); in si_vce_send_vcepll_ctlreq()
1904 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL_2, in si_set_vce_clocks()
1909 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, VCEPLL_BYPASS_EN_MASK, in si_set_vce_clocks()
1914 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, VCEPLL_SLEEP_MASK, in si_set_vce_clocks()
1926 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL_5, 0, ~RESET_ANTI_MUX_MASK); in si_set_vce_clocks()
1929 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, VCEPLL_VCO_MODE_MASK, in si_set_vce_clocks()
1933 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, VCEPLL_SLEEP_MASK, in si_set_vce_clocks()
1935 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_SLEEP_MASK); in si_set_vce_clocks()
1938 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_RESET_MASK); in si_set_vce_clocks()
1947 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, VCEPLL_RESET_MASK, ~VCEPLL_RESET_MASK); in si_set_vce_clocks()
1950 WREG32_SMC_P(CG_VCEPLL_SPREAD_SPECTRUM, 0, ~SSEN_MASK); in si_set_vce_clocks()
1953 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL_3, in si_set_vce_clocks()
1958 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_REF_DIV_MASK); in si_set_vce_clocks()
1961 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL_2, in si_set_vce_clocks()
1969 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_RESET_MASK); in si_set_vce_clocks()
1974 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_BYPASS_EN_MASK); in si_set_vce_clocks()
1981 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL_2, in si_set_vce_clocks()