Lines Matching refs:ib
64 struct amdgpu_ib *ib, in si_dma_ring_emit_ib() argument
74 amdgpu_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0)); in si_dma_ring_emit_ib()
75 amdgpu_ring_write(ring, (ib->length_dw << 12) | (upper_32_bits(ib->gpu_addr) & 0xFF)); in si_dma_ring_emit_ib()
253 struct amdgpu_ib ib; in si_dma_ring_test_ib() local
267 memset(&ib, 0, sizeof(ib)); in si_dma_ring_test_ib()
269 AMDGPU_IB_POOL_DIRECT, &ib); in si_dma_ring_test_ib()
273 ib.ptr[0] = DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 0, 1); in si_dma_ring_test_ib()
274 ib.ptr[1] = lower_32_bits(gpu_addr); in si_dma_ring_test_ib()
275 ib.ptr[2] = upper_32_bits(gpu_addr) & 0xff; in si_dma_ring_test_ib()
276 ib.ptr[3] = 0xDEADBEEF; in si_dma_ring_test_ib()
277 ib.length_dw = 4; in si_dma_ring_test_ib()
278 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); in si_dma_ring_test_ib()
296 amdgpu_ib_free(adev, &ib, NULL); in si_dma_ring_test_ib()
313 static void si_dma_vm_copy_pte(struct amdgpu_ib *ib, in si_dma_vm_copy_pte() argument
319 ib->ptr[ib->length_dw++] = DMA_PACKET(DMA_PACKET_COPY, in si_dma_vm_copy_pte()
321 ib->ptr[ib->length_dw++] = lower_32_bits(pe); in si_dma_vm_copy_pte()
322 ib->ptr[ib->length_dw++] = lower_32_bits(src); in si_dma_vm_copy_pte()
323 ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff; in si_dma_vm_copy_pte()
324 ib->ptr[ib->length_dw++] = upper_32_bits(src) & 0xff; in si_dma_vm_copy_pte()
338 static void si_dma_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, in si_dma_vm_write_pte() argument
344 ib->ptr[ib->length_dw++] = DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 0, ndw); in si_dma_vm_write_pte()
345 ib->ptr[ib->length_dw++] = lower_32_bits(pe); in si_dma_vm_write_pte()
346 ib->ptr[ib->length_dw++] = upper_32_bits(pe); in si_dma_vm_write_pte()
348 ib->ptr[ib->length_dw++] = lower_32_bits(value); in si_dma_vm_write_pte()
349 ib->ptr[ib->length_dw++] = upper_32_bits(value); in si_dma_vm_write_pte()
366 static void si_dma_vm_set_pte_pde(struct amdgpu_ib *ib, in si_dma_vm_set_pte_pde() argument
385 ib->ptr[ib->length_dw++] = DMA_PTE_PDE_PACKET(ndw); in si_dma_vm_set_pte_pde()
386 ib->ptr[ib->length_dw++] = pe; /* dst addr */ in si_dma_vm_set_pte_pde()
387 ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff; in si_dma_vm_set_pte_pde()
388 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ in si_dma_vm_set_pte_pde()
389 ib->ptr[ib->length_dw++] = upper_32_bits(flags); in si_dma_vm_set_pte_pde()
390 ib->ptr[ib->length_dw++] = value; /* value */ in si_dma_vm_set_pte_pde()
391 ib->ptr[ib->length_dw++] = upper_32_bits(value); in si_dma_vm_set_pte_pde()
392 ib->ptr[ib->length_dw++] = incr; /* increment size */ in si_dma_vm_set_pte_pde()
393 ib->ptr[ib->length_dw++] = 0; in si_dma_vm_set_pte_pde()
407 static void si_dma_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) in si_dma_ring_pad_ib() argument
409 while (ib->length_dw & 0x7) in si_dma_ring_pad_ib()
410 ib->ptr[ib->length_dw++] = DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0); in si_dma_ring_pad_ib()
777 static void si_dma_emit_copy_buffer(struct amdgpu_ib *ib, in si_dma_emit_copy_buffer() argument
783 ib->ptr[ib->length_dw++] = DMA_PACKET(DMA_PACKET_COPY, in si_dma_emit_copy_buffer()
785 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); in si_dma_emit_copy_buffer()
786 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); in si_dma_emit_copy_buffer()
787 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset) & 0xff; in si_dma_emit_copy_buffer()
788 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset) & 0xff; in si_dma_emit_copy_buffer()
801 static void si_dma_emit_fill_buffer(struct amdgpu_ib *ib, in si_dma_emit_fill_buffer() argument
806 ib->ptr[ib->length_dw++] = DMA_PACKET(DMA_PACKET_CONSTANT_FILL, in si_dma_emit_fill_buffer()
808 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); in si_dma_emit_fill_buffer()
809 ib->ptr[ib->length_dw++] = src_data; in si_dma_emit_fill_buffer()
810 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset) << 16; in si_dma_emit_fill_buffer()