Lines Matching refs:sdma_offsets
30 const u32 sdma_offsets[SDMA_MAX_INSTANCE] = variable
51 return (RREG32(DMA_RB_WPTR + sdma_offsets[me]) & 0x3fffc) >> 2; in si_dma_ring_get_wptr()
59 WREG32(DMA_RB_WPTR + sdma_offsets[me], (ring->wptr << 2) & 0x3fffc); in si_dma_ring_set_wptr()
122 rb_cntl = RREG32(DMA_RB_CNTL + sdma_offsets[i]); in si_dma_stop()
124 WREG32(DMA_RB_CNTL + sdma_offsets[i], rb_cntl); in si_dma_stop()
138 WREG32(DMA_SEM_INCOMPLETE_TIMER_CNTL + sdma_offsets[i], 0); in si_dma_start()
139 WREG32(DMA_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0); in si_dma_start()
147 WREG32(DMA_RB_CNTL + sdma_offsets[i], rb_cntl); in si_dma_start()
150 WREG32(DMA_RB_RPTR + sdma_offsets[i], 0); in si_dma_start()
151 WREG32(DMA_RB_WPTR + sdma_offsets[i], 0); in si_dma_start()
155 WREG32(DMA_RB_RPTR_ADDR_LO + sdma_offsets[i], lower_32_bits(rptr_addr)); in si_dma_start()
156 WREG32(DMA_RB_RPTR_ADDR_HI + sdma_offsets[i], upper_32_bits(rptr_addr) & 0xFF); in si_dma_start()
160 WREG32(DMA_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8); in si_dma_start()
167 WREG32(DMA_IB_CNTL + sdma_offsets[i], ib_cntl); in si_dma_start()
169 dma_cntl = RREG32(DMA_CNTL + sdma_offsets[i]); in si_dma_start()
171 WREG32(DMA_CNTL + sdma_offsets[i], dma_cntl); in si_dma_start()
174 WREG32(DMA_RB_WPTR + sdma_offsets[i], ring->wptr << 2); in si_dma_start()
175 WREG32(DMA_RB_CNTL + sdma_offsets[i], rb_cntl | DMA_RB_ENABLE); in si_dma_start()