Lines Matching refs:PACKET0
94 amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_BASE, 0)); in uvd_v3_1_ring_emit_ib()
96 amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_SIZE, 0)); in uvd_v3_1_ring_emit_ib()
115 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); in uvd_v3_1_ring_emit_fence()
117 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); in uvd_v3_1_ring_emit_fence()
119 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); in uvd_v3_1_ring_emit_fence()
121 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); in uvd_v3_1_ring_emit_fence()
124 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); in uvd_v3_1_ring_emit_fence()
126 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); in uvd_v3_1_ring_emit_fence()
128 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); in uvd_v3_1_ring_emit_fence()
151 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); in uvd_v3_1_ring_test_ring()
174 amdgpu_ring_write(ring, PACKET0(mmUVD_NO_OP, 0)); in uvd_v3_1_ring_insert_nop()
662 tmp = PACKET0(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0); in uvd_v3_1_hw_init()
666 tmp = PACKET0(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0); in uvd_v3_1_hw_init()
670 tmp = PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0); in uvd_v3_1_hw_init()
675 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0)); in uvd_v3_1_hw_init()
678 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0)); in uvd_v3_1_hw_init()