Lines Matching refs:PACKET0
485 tmp = PACKET0(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0); in uvd_v6_0_hw_init()
489 tmp = PACKET0(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0); in uvd_v6_0_hw_init()
493 tmp = PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0); in uvd_v6_0_hw_init()
498 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0)); in uvd_v6_0_hw_init()
501 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0)); in uvd_v6_0_hw_init()
924 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); in uvd_v6_0_ring_emit_fence()
926 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); in uvd_v6_0_ring_emit_fence()
928 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); in uvd_v6_0_ring_emit_fence()
930 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); in uvd_v6_0_ring_emit_fence()
933 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); in uvd_v6_0_ring_emit_fence()
935 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); in uvd_v6_0_ring_emit_fence()
937 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); in uvd_v6_0_ring_emit_fence()
992 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); in uvd_v6_0_ring_test_ring()
1025 amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_VMID, 0)); in uvd_v6_0_ring_emit_ib()
1028 amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_LOW, 0)); in uvd_v6_0_ring_emit_ib()
1030 amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH, 0)); in uvd_v6_0_ring_emit_ib()
1032 amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_SIZE, 0)); in uvd_v6_0_ring_emit_ib()
1063 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); in uvd_v6_0_ring_emit_wreg()
1065 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); in uvd_v6_0_ring_emit_wreg()
1067 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); in uvd_v6_0_ring_emit_wreg()
1076 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); in uvd_v6_0_ring_emit_vm_flush()
1078 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); in uvd_v6_0_ring_emit_vm_flush()
1080 amdgpu_ring_write(ring, PACKET0(mmUVD_GP_SCRATCH8, 0)); in uvd_v6_0_ring_emit_vm_flush()
1082 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); in uvd_v6_0_ring_emit_vm_flush()
1091 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); in uvd_v6_0_ring_emit_pipeline_sync()
1093 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); in uvd_v6_0_ring_emit_pipeline_sync()
1095 amdgpu_ring_write(ring, PACKET0(mmUVD_GP_SCRATCH8, 0)); in uvd_v6_0_ring_emit_pipeline_sync()
1097 amdgpu_ring_write(ring, PACKET0(mmUVD_GP_SCRATCH9, 0)); in uvd_v6_0_ring_emit_pipeline_sync()
1099 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); in uvd_v6_0_ring_emit_pipeline_sync()
1110 amdgpu_ring_write(ring, PACKET0(mmUVD_NO_OP, 0)); in uvd_v6_0_ring_insert_nop()