Lines Matching refs:vce
183 WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR, (adev->vce.gpu_addr >> 8)); in vce_v2_0_mc_resume()
243 ring = &adev->vce.ring[0]; in vce_v2_0_start()
250 ring = &adev->vce.ring[1]; in vce_v2_0_start()
405 adev->vce.num_rings = 2; in vce_v2_0_early_init()
420 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 167, &adev->vce.irq); in vce_v2_0_sw_init()
433 for (i = 0; i < adev->vce.num_rings; i++) { in vce_v2_0_sw_init()
436 ring = &adev->vce.ring[i]; in vce_v2_0_sw_init()
438 r = amdgpu_ring_init(adev, ring, 512, &adev->vce.irq, 0, in vce_v2_0_sw_init()
469 for (i = 0; i < adev->vce.num_rings; i++) { in vce_v2_0_hw_init()
470 r = amdgpu_ring_test_helper(&adev->vce.ring[i]); in vce_v2_0_hw_init()
484 cancel_delayed_work_sync(&adev->vce.idle_work); in vce_v2_0_hw_fini()
506 cancel_delayed_work_sync(&adev->vce.idle_work); in vce_v2_0_suspend()
569 amdgpu_fence_process(&adev->vce.ring[entry->src_data[0]]); in vce_v2_0_process_interrupt()
659 for (i = 0; i < adev->vce.num_rings; i++) { in vce_v2_0_set_ring_funcs()
660 adev->vce.ring[i].funcs = &vce_v2_0_ring_funcs; in vce_v2_0_set_ring_funcs()
661 adev->vce.ring[i].me = i; in vce_v2_0_set_ring_funcs()
672 adev->vce.irq.num_types = 1; in vce_v2_0_set_irq_funcs()
673 adev->vce.irq.funcs = &vce_v2_0_irq_funcs; in vce_v2_0_set_irq_funcs()