Lines Matching refs:vce

179 	WDOORBELL32(adev->vce.ring[0].doorbell_index, 0);  in vce_v4_0_mmsch_start()
180 *adev->vce.ring[0].wptr_cpu_addr = 0; in vce_v4_0_mmsch_start()
181 adev->vce.ring[0].wptr = 0; in vce_v4_0_mmsch_start()
182 adev->vce.ring[0].wptr_old = 0; in vce_v4_0_mmsch_start()
233 ring = &adev->vce.ring[0]; in vce_v4_0_sriov_start()
263 adev->vce.gpu_addr >> 8); in vce_v4_0_sriov_start()
266 (adev->vce.gpu_addr >> 40) & 0xff); in vce_v4_0_sriov_start()
273 adev->vce.gpu_addr >> 8); in vce_v4_0_sriov_start()
276 (adev->vce.gpu_addr >> 40) & 0xff); in vce_v4_0_sriov_start()
279 adev->vce.gpu_addr >> 8); in vce_v4_0_sriov_start()
282 (adev->vce.gpu_addr >> 40) & 0xff); in vce_v4_0_sriov_start()
341 ring = &adev->vce.ring[0]; in vce_v4_0_start()
349 ring = &adev->vce.ring[1]; in vce_v4_0_start()
357 ring = &adev->vce.ring[2]; in vce_v4_0_start()
415 adev->vce.num_rings = 1; in vce_v4_0_early_init()
417 adev->vce.num_rings = 3; in vce_v4_0_early_init()
433 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCE0, 167, &adev->vce.irq); in vce_v4_0_sw_init()
447 unsigned size = amdgpu_bo_size(adev->vce.vcpu_bo); in vce_v4_0_sw_init()
449 adev->vce.saved_bo = kvmalloc(size, GFP_KERNEL); in vce_v4_0_sw_init()
450 if (!adev->vce.saved_bo) in vce_v4_0_sw_init()
453 hdr = (const struct common_firmware_header *)adev->vce.fw->data; in vce_v4_0_sw_init()
455 adev->firmware.ucode[AMDGPU_UCODE_ID_VCE].fw = adev->vce.fw; in vce_v4_0_sw_init()
465 for (i = 0; i < adev->vce.num_rings; i++) { in vce_v4_0_sw_init()
468 ring = &adev->vce.ring[i]; in vce_v4_0_sw_init()
482 r = amdgpu_ring_init(adev, ring, 512, &adev->vce.irq, 0, in vce_v4_0_sw_init()
509 kvfree(adev->vce.saved_bo); in vce_v4_0_sw_fini()
510 adev->vce.saved_bo = NULL; in vce_v4_0_sw_fini()
532 for (i = 0; i < adev->vce.num_rings; i++) { in vce_v4_0_hw_init()
533 r = amdgpu_ring_test_helper(&adev->vce.ring[i]); in vce_v4_0_hw_init()
547 cancel_delayed_work_sync(&adev->vce.idle_work); in vce_v4_0_hw_fini()
565 if (adev->vce.vcpu_bo == NULL) in vce_v4_0_suspend()
570 unsigned size = amdgpu_bo_size(adev->vce.vcpu_bo); in vce_v4_0_suspend()
571 void *ptr = adev->vce.cpu_addr; in vce_v4_0_suspend()
573 memcpy_fromio(adev->vce.saved_bo, ptr, size); in vce_v4_0_suspend()
589 cancel_delayed_work_sync(&adev->vce.idle_work); in vce_v4_0_suspend()
613 if (adev->vce.vcpu_bo == NULL) in vce_v4_0_resume()
619 unsigned size = amdgpu_bo_size(adev->vce.vcpu_bo); in vce_v4_0_resume()
620 void *ptr = adev->vce.cpu_addr; in vce_v4_0_resume()
622 memcpy_toio(ptr, adev->vce.saved_bo, size); in vce_v4_0_resume()
662 (adev->vce.gpu_addr >> 8)); in vce_v4_0_mc_resume()
664 (adev->vce.gpu_addr >> 40) & 0xff); in vce_v4_0_mc_resume()
671 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_40BIT_BAR1), (adev->vce.gpu_addr >> 8)); in vce_v4_0_mc_resume()
672 …WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_64BIT_BAR1), (adev->vce.gpu_addr >> 40) & 0xf… in vce_v4_0_mc_resume()
678 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_40BIT_BAR2), (adev->vce.gpu_addr >> 8)); in vce_v4_0_mc_resume()
679 …WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_64BIT_BAR2), (adev->vce.gpu_addr >> 40) & 0xf… in vce_v4_0_mc_resume()
704 mask |= (adev->vce.harvest_config & AMDGPU_VCE_HARVEST_VCE0) ? 0 : SRBM_STATUS2__VCE0_BUSY_MASK;
705 mask |= (adev->vce.harvest_config & AMDGPU_VCE_HARVEST_VCE1) ? 0 : SRBM_STATUS2__VCE1_BUSY_MASK;
761 adev->vce.srbm_soft_reset = srbm_soft_reset;
764 adev->vce.srbm_soft_reset = 0;
774 if (!adev->vce.srbm_soft_reset)
776 srbm_soft_reset = adev->vce.srbm_soft_reset;
804 if (!adev->vce.srbm_soft_reset)
817 if (!adev->vce.srbm_soft_reset)
936 if (adev->vce.harvest_config & (1 << i))
1069 amdgpu_fence_process(&adev->vce.ring[entry->src_data[0]]); in vce_v4_0_process_interrupt()
1137 for (i = 0; i < adev->vce.num_rings; i++) { in vce_v4_0_set_ring_funcs()
1138 adev->vce.ring[i].funcs = &vce_v4_0_ring_vm_funcs; in vce_v4_0_set_ring_funcs()
1139 adev->vce.ring[i].me = i; in vce_v4_0_set_ring_funcs()
1151 adev->vce.irq.num_types = 1; in vce_v4_0_set_irq_funcs()
1152 adev->vce.irq.funcs = &vce_v4_0_irq_funcs; in vce_v4_0_set_irq_funcs()