Lines Matching refs:vcn
77 adev->vcn.num_enc_rings = 1; in vcn_v2_0_early_init()
79 adev->vcn.num_enc_rings = 2; in vcn_v2_0_early_init()
105 &adev->vcn.inst->irq); in vcn_v2_0_sw_init()
110 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { in vcn_v2_0_sw_init()
113 &adev->vcn.inst->irq); in vcn_v2_0_sw_init()
128 ring = &adev->vcn.inst->ring_dec; in vcn_v2_0_sw_init()
131 ring->doorbell_index = adev->doorbell_index.vcn.vcn_ring0_1 << 1; in vcn_v2_0_sw_init()
134 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0, in vcn_v2_0_sw_init()
139 adev->vcn.internal.context_id = mmUVD_CONTEXT_ID_INTERNAL_OFFSET; in vcn_v2_0_sw_init()
140 adev->vcn.internal.ib_vmid = mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET; in vcn_v2_0_sw_init()
141 adev->vcn.internal.ib_bar_low = mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET; in vcn_v2_0_sw_init()
142 adev->vcn.internal.ib_bar_high = mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET; in vcn_v2_0_sw_init()
143 adev->vcn.internal.ib_size = mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET; in vcn_v2_0_sw_init()
144 adev->vcn.internal.gp_scratch8 = mmUVD_GP_SCRATCH8_INTERNAL_OFFSET; in vcn_v2_0_sw_init()
146 adev->vcn.internal.scratch9 = mmUVD_SCRATCH9_INTERNAL_OFFSET; in vcn_v2_0_sw_init()
147 adev->vcn.inst->external.scratch9 = SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9); in vcn_v2_0_sw_init()
148 adev->vcn.internal.data0 = mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET; in vcn_v2_0_sw_init()
149 adev->vcn.inst->external.data0 = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0); in vcn_v2_0_sw_init()
150 adev->vcn.internal.data1 = mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET; in vcn_v2_0_sw_init()
151 adev->vcn.inst->external.data1 = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1); in vcn_v2_0_sw_init()
152 adev->vcn.internal.cmd = mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET; in vcn_v2_0_sw_init()
153 adev->vcn.inst->external.cmd = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD); in vcn_v2_0_sw_init()
154 adev->vcn.internal.nop = mmUVD_NO_OP_INTERNAL_OFFSET; in vcn_v2_0_sw_init()
155 adev->vcn.inst->external.nop = SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP); in vcn_v2_0_sw_init()
157 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { in vcn_v2_0_sw_init()
160 ring = &adev->vcn.inst->ring_enc[i]; in vcn_v2_0_sw_init()
163 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + i; in vcn_v2_0_sw_init()
165 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1 + i; in vcn_v2_0_sw_init()
167 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0, in vcn_v2_0_sw_init()
173 adev->vcn.pause_dpg_mode = vcn_v2_0_pause_dpg_mode; in vcn_v2_0_sw_init()
179 fw_shared = adev->vcn.inst->fw_shared.cpu_addr; in vcn_v2_0_sw_init()
183 amdgpu_vcn_fwlog_init(adev->vcn.inst); in vcn_v2_0_sw_init()
199 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared.cpu_addr; in vcn_v2_0_sw_fini()
227 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec; in vcn_v2_0_hw_init()
244 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { in vcn_v2_0_hw_init()
245 ring = &adev->vcn.inst->ring_enc[i]; in vcn_v2_0_hw_init()
270 cancel_delayed_work_sync(&adev->vcn.idle_work); in vcn_v2_0_hw_fini()
273 (adev->vcn.cur_state != AMD_PG_STATE_GATE && in vcn_v2_0_hw_fini()
331 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); in vcn_v2_0_mc_resume()
347 lower_32_bits(adev->vcn.inst->gpu_addr)); in vcn_v2_0_mc_resume()
349 upper_32_bits(adev->vcn.inst->gpu_addr)); in vcn_v2_0_mc_resume()
359 lower_32_bits(adev->vcn.inst->gpu_addr + offset)); in vcn_v2_0_mc_resume()
361 upper_32_bits(adev->vcn.inst->gpu_addr + offset)); in vcn_v2_0_mc_resume()
367 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); in vcn_v2_0_mc_resume()
369 upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); in vcn_v2_0_mc_resume()
375 lower_32_bits(adev->vcn.inst->fw_shared.gpu_addr)); in vcn_v2_0_mc_resume()
377 upper_32_bits(adev->vcn.inst->fw_shared.gpu_addr)); in vcn_v2_0_mc_resume()
387 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); in vcn_v2_0_mc_resume_dpg_mode()
413 lower_32_bits(adev->vcn.inst->gpu_addr), 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
416 upper_32_bits(adev->vcn.inst->gpu_addr), 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
434 lower_32_bits(adev->vcn.inst->gpu_addr + offset), 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
437 upper_32_bits(adev->vcn.inst->gpu_addr + offset), 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
454 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
457 upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
466 lower_32_bits(adev->vcn.inst->fw_shared.gpu_addr), 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
469 upper_32_bits(adev->vcn.inst->fw_shared.gpu_addr), 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
795 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared.cpu_addr; in vcn_v2_0_start_dpg_mode()
796 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec; in vcn_v2_0_start_dpg_mode()
808 adev->vcn.inst->dpg_sram_curr_addr = (uint32_t *)adev->vcn.inst->dpg_sram_cpu_addr; in vcn_v2_0_start_dpg_mode()
882 psp_update_vcn_sram(adev, 0, adev->vcn.inst->dpg_sram_gpu_addr, in vcn_v2_0_start_dpg_mode()
883 (uint32_t)((uintptr_t)adev->vcn.inst->dpg_sram_curr_addr - in vcn_v2_0_start_dpg_mode()
884 (uintptr_t)adev->vcn.inst->dpg_sram_cpu_addr)); in vcn_v2_0_start_dpg_mode()
932 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared.cpu_addr; in vcn_v2_0_start()
933 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec; in vcn_v2_0_start()
942 return vcn_v2_0_start_dpg_mode(adev, adev->vcn.indirect_sram); in vcn_v2_0_start()
1083 ring = &adev->vcn.inst->ring_enc[0]; in vcn_v2_0_start()
1092 ring = &adev->vcn.inst->ring_enc[1]; in vcn_v2_0_start()
1209 if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) { in vcn_v2_0_pause_dpg_mode()
1211 adev->vcn.inst[inst_idx].pause_state.fw_based, new_state->fw_based); in vcn_v2_0_pause_dpg_mode()
1220 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared.cpu_addr; in vcn_v2_0_pause_dpg_mode()
1236 ring = &adev->vcn.inst->ring_enc[0]; in vcn_v2_0_pause_dpg_mode()
1246 ring = &adev->vcn.inst->ring_enc[1]; in vcn_v2_0_pause_dpg_mode()
1272 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based; in vcn_v2_0_pause_dpg_mode()
1382 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0)); in vcn_v2_0_dec_ring_insert_start()
1384 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0)); in vcn_v2_0_dec_ring_insert_start()
1399 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0)); in vcn_v2_0_dec_ring_insert_end()
1419 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.nop, 0)); in vcn_v2_0_dec_ring_insert_nop()
1440 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.context_id, 0)); in vcn_v2_0_dec_ring_emit_fence()
1443 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0)); in vcn_v2_0_dec_ring_emit_fence()
1446 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data1, 0)); in vcn_v2_0_dec_ring_emit_fence()
1449 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0)); in vcn_v2_0_dec_ring_emit_fence()
1452 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0)); in vcn_v2_0_dec_ring_emit_fence()
1455 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data1, 0)); in vcn_v2_0_dec_ring_emit_fence()
1458 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0)); in vcn_v2_0_dec_ring_emit_fence()
1481 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.ib_vmid, 0)); in vcn_v2_0_dec_ring_emit_ib()
1484 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.ib_bar_low, 0)); in vcn_v2_0_dec_ring_emit_ib()
1486 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.ib_bar_high, 0)); in vcn_v2_0_dec_ring_emit_ib()
1488 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.ib_size, 0)); in vcn_v2_0_dec_ring_emit_ib()
1497 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0)); in vcn_v2_0_dec_ring_emit_reg_wait()
1500 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data1, 0)); in vcn_v2_0_dec_ring_emit_reg_wait()
1503 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.gp_scratch8, 0)); in vcn_v2_0_dec_ring_emit_reg_wait()
1506 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0)); in vcn_v2_0_dec_ring_emit_reg_wait()
1531 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0)); in vcn_v2_0_dec_ring_emit_wreg()
1534 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data1, 0)); in vcn_v2_0_dec_ring_emit_wreg()
1537 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0)); in vcn_v2_0_dec_ring_emit_wreg()
1553 if (ring == &adev->vcn.inst->ring_enc[0]) in vcn_v2_0_enc_ring_get_rptr()
1570 if (ring == &adev->vcn.inst->ring_enc[0]) { in vcn_v2_0_enc_ring_get_wptr()
1594 if (ring == &adev->vcn.inst->ring_enc[0]) { in vcn_v2_0_enc_ring_set_wptr()
1707 amdgpu_fence_process(&adev->vcn.inst->ring_dec); in vcn_v2_0_process_interrupt()
1710 amdgpu_fence_process(&adev->vcn.inst->ring_enc[0]); in vcn_v2_0_process_interrupt()
1713 amdgpu_fence_process(&adev->vcn.inst->ring_enc[1]); in vcn_v2_0_process_interrupt()
1734 WREG32(adev->vcn.inst[ring->me].external.scratch9, 0xCAFEDEAD); in vcn_v2_0_dec_ring_test_ring()
1738 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0)); in vcn_v2_0_dec_ring_test_ring()
1740 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.scratch9, 0)); in vcn_v2_0_dec_ring_test_ring()
1744 tmp = RREG32(adev->vcn.inst[ring->me].external.scratch9); in vcn_v2_0_dec_ring_test_ring()
1771 adev->vcn.cur_state = AMD_PG_STATE_UNGATE; in vcn_v2_0_set_powergating_state()
1775 if (state == adev->vcn.cur_state) in vcn_v2_0_set_powergating_state()
1784 adev->vcn.cur_state = state; in vcn_v2_0_set_powergating_state()
1819 adev->vcn.inst->ring_dec.wptr = 0; in vcn_v2_0_start_mmsch()
1820 adev->vcn.inst->ring_dec.wptr_old = 0; in vcn_v2_0_start_mmsch()
1821 vcn_v2_0_dec_ring_set_wptr(&adev->vcn.inst->ring_dec); in vcn_v2_0_start_mmsch()
1823 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { in vcn_v2_0_start_mmsch()
1824 adev->vcn.inst->ring_enc[i].wptr = 0; in vcn_v2_0_start_mmsch()
1825 adev->vcn.inst->ring_enc[i].wptr_old = 0; in vcn_v2_0_start_mmsch()
1826 vcn_v2_0_enc_ring_set_wptr(&adev->vcn.inst->ring_enc[i]); in vcn_v2_0_start_mmsch()
1881 size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); in vcn_v2_0_start_sriov()
1902 lower_32_bits(adev->vcn.inst->gpu_addr)); in vcn_v2_0_start_sriov()
1906 upper_32_bits(adev->vcn.inst->gpu_addr)); in vcn_v2_0_start_sriov()
1920 lower_32_bits(adev->vcn.inst->gpu_addr + offset)); in vcn_v2_0_start_sriov()
1924 upper_32_bits(adev->vcn.inst->gpu_addr + offset)); in vcn_v2_0_start_sriov()
1935 lower_32_bits(adev->vcn.inst->gpu_addr + offset + in vcn_v2_0_start_sriov()
1940 upper_32_bits(adev->vcn.inst->gpu_addr + offset + in vcn_v2_0_start_sriov()
1949 for (r = 0; r < adev->vcn.num_enc_rings; ++r) { in vcn_v2_0_start_sriov()
1950 ring = &adev->vcn.inst->ring_enc[r]; in vcn_v2_0_start_sriov()
1963 ring = &adev->vcn.inst->ring_dec; in vcn_v2_0_start_sriov()
2076 adev->vcn.inst->ring_dec.funcs = &vcn_v2_0_dec_ring_vm_funcs; in vcn_v2_0_set_dec_ring_funcs()
2084 for (i = 0; i < adev->vcn.num_enc_rings; ++i) in vcn_v2_0_set_enc_ring_funcs()
2085 adev->vcn.inst->ring_enc[i].funcs = &vcn_v2_0_enc_ring_vm_funcs; in vcn_v2_0_set_enc_ring_funcs()
2097 adev->vcn.inst->irq.num_types = adev->vcn.num_enc_rings + 1; in vcn_v2_0_set_irq_funcs()
2098 adev->vcn.inst->irq.funcs = &vcn_v2_0_irq_funcs; in vcn_v2_0_set_irq_funcs()