Lines Matching refs:ih_regs
52 struct amdgpu_ih_regs *ih_regs; in vega20_ih_init_register_offset() local
55 ih_regs = &adev->irq.ih.ih_regs; in vega20_ih_init_register_offset()
56 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE); in vega20_ih_init_register_offset()
57 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI); in vega20_ih_init_register_offset()
58 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL); in vega20_ih_init_register_offset()
59 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR); in vega20_ih_init_register_offset()
60 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR); in vega20_ih_init_register_offset()
61 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR); in vega20_ih_init_register_offset()
62 ih_regs->ih_rb_wptr_addr_lo = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO); in vega20_ih_init_register_offset()
63 ih_regs->ih_rb_wptr_addr_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI); in vega20_ih_init_register_offset()
64 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL; in vega20_ih_init_register_offset()
68 ih_regs = &adev->irq.ih1.ih_regs; in vega20_ih_init_register_offset()
69 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING1); in vega20_ih_init_register_offset()
70 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING1); in vega20_ih_init_register_offset()
71 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING1); in vega20_ih_init_register_offset()
72 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING1); in vega20_ih_init_register_offset()
73 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING1); in vega20_ih_init_register_offset()
74 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING1); in vega20_ih_init_register_offset()
75 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING1; in vega20_ih_init_register_offset()
79 ih_regs = &adev->irq.ih2.ih_regs; in vega20_ih_init_register_offset()
80 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING2); in vega20_ih_init_register_offset()
81 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING2); in vega20_ih_init_register_offset()
82 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING2); in vega20_ih_init_register_offset()
83 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING2); in vega20_ih_init_register_offset()
84 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING2); in vega20_ih_init_register_offset()
85 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING2); in vega20_ih_init_register_offset()
86 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING2; in vega20_ih_init_register_offset()
103 struct amdgpu_ih_regs *ih_regs; in vega20_ih_toggle_ring_interrupts() local
106 ih_regs = &ih->ih_regs; in vega20_ih_toggle_ring_interrupts()
108 tmp = RREG32(ih_regs->ih_rb_cntl); in vega20_ih_toggle_ring_interrupts()
116 if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) { in vega20_ih_toggle_ring_interrupts()
121 WREG32(ih_regs->ih_rb_cntl, tmp); in vega20_ih_toggle_ring_interrupts()
128 WREG32(ih_regs->ih_rb_rptr, 0); in vega20_ih_toggle_ring_interrupts()
129 WREG32(ih_regs->ih_rb_wptr, 0); in vega20_ih_toggle_ring_interrupts()
215 struct amdgpu_ih_regs *ih_regs; in vega20_ih_enable_ring() local
218 ih_regs = &ih->ih_regs; in vega20_ih_enable_ring()
221 WREG32(ih_regs->ih_rb_base, ih->gpu_addr >> 8); in vega20_ih_enable_ring()
222 WREG32(ih_regs->ih_rb_base_hi, (ih->gpu_addr >> 40) & 0xff); in vega20_ih_enable_ring()
224 tmp = RREG32(ih_regs->ih_rb_cntl); in vega20_ih_enable_ring()
231 if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) { in vega20_ih_enable_ring()
236 WREG32(ih_regs->ih_rb_cntl, tmp); in vega20_ih_enable_ring()
241 WREG32(ih_regs->ih_rb_wptr_addr_lo, lower_32_bits(ih->wptr_addr)); in vega20_ih_enable_ring()
242 WREG32(ih_regs->ih_rb_wptr_addr_hi, upper_32_bits(ih->wptr_addr) & 0xFFFF); in vega20_ih_enable_ring()
246 WREG32(ih_regs->ih_rb_wptr, 0); in vega20_ih_enable_ring()
247 WREG32(ih_regs->ih_rb_rptr, 0); in vega20_ih_enable_ring()
249 WREG32(ih_regs->ih_doorbell_rptr, vega20_ih_doorbell_rptr(ih)); in vega20_ih_enable_ring()
390 struct amdgpu_ih_regs *ih_regs; in vega20_ih_get_wptr() local
404 ih_regs = &ih->ih_regs; in vega20_ih_get_wptr()
407 wptr = RREG32_NO_KIQ(ih_regs->ih_rb_wptr); in vega20_ih_get_wptr()
423 tmp = RREG32_NO_KIQ(ih_regs->ih_rb_cntl); in vega20_ih_get_wptr()
425 WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp); in vega20_ih_get_wptr()
443 struct amdgpu_ih_regs *ih_regs; in vega20_ih_irq_rearm() local
445 ih_regs = &ih->ih_regs; in vega20_ih_irq_rearm()
449 v = RREG32_NO_KIQ(ih_regs->ih_rb_rptr); in vega20_ih_irq_rearm()
468 struct amdgpu_ih_regs *ih_regs; in vega20_ih_set_rptr() local
481 ih_regs = &ih->ih_regs; in vega20_ih_set_rptr()
482 WREG32(ih_regs->ih_rb_rptr, ih->rptr); in vega20_ih_set_rptr()