Lines Matching refs:adev
36 #define amdgpu_dpm_enable_bapm(adev, e) \ argument
37 ((adev)->powerplay.pp_funcs->enable_bapm((adev)->powerplay.pp_handle, (e)))
39 int amdgpu_dpm_get_sclk(struct amdgpu_device *adev, bool low) in amdgpu_dpm_get_sclk() argument
41 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_get_sclk()
47 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_sclk()
48 ret = pp_funcs->get_sclk((adev)->powerplay.pp_handle, in amdgpu_dpm_get_sclk()
50 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_sclk()
55 int amdgpu_dpm_get_mclk(struct amdgpu_device *adev, bool low) in amdgpu_dpm_get_mclk() argument
57 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_get_mclk()
63 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_mclk()
64 ret = pp_funcs->get_mclk((adev)->powerplay.pp_handle, in amdgpu_dpm_get_mclk()
66 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_mclk()
71 int amdgpu_dpm_set_powergating_by_smu(struct amdgpu_device *adev, uint32_t block_type, bool gate) in amdgpu_dpm_set_powergating_by_smu() argument
74 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_set_powergating_by_smu()
77 if (atomic_read(&adev->pm.pwr_state[block_type]) == pwr_state) { in amdgpu_dpm_set_powergating_by_smu()
78 dev_dbg(adev->dev, "IP block%d already in the target %s state!", in amdgpu_dpm_set_powergating_by_smu()
83 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_set_powergating_by_smu()
96 (adev)->powerplay.pp_handle, block_type, gate)); in amdgpu_dpm_set_powergating_by_smu()
103 atomic_set(&adev->pm.pwr_state[block_type], pwr_state); in amdgpu_dpm_set_powergating_by_smu()
105 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_set_powergating_by_smu()
110 int amdgpu_dpm_set_gfx_power_up_by_imu(struct amdgpu_device *adev) in amdgpu_dpm_set_gfx_power_up_by_imu() argument
112 struct smu_context *smu = adev->powerplay.pp_handle; in amdgpu_dpm_set_gfx_power_up_by_imu()
115 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_set_gfx_power_up_by_imu()
117 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_set_gfx_power_up_by_imu()
124 int amdgpu_dpm_baco_enter(struct amdgpu_device *adev) in amdgpu_dpm_baco_enter() argument
126 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_baco_enter()
127 void *pp_handle = adev->powerplay.pp_handle; in amdgpu_dpm_baco_enter()
133 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_baco_enter()
138 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_baco_enter()
143 int amdgpu_dpm_baco_exit(struct amdgpu_device *adev) in amdgpu_dpm_baco_exit() argument
145 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_baco_exit()
146 void *pp_handle = adev->powerplay.pp_handle; in amdgpu_dpm_baco_exit()
152 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_baco_exit()
157 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_baco_exit()
162 int amdgpu_dpm_set_mp1_state(struct amdgpu_device *adev, in amdgpu_dpm_set_mp1_state() argument
166 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_set_mp1_state()
169 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_set_mp1_state()
172 adev->powerplay.pp_handle, in amdgpu_dpm_set_mp1_state()
175 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_set_mp1_state()
181 bool amdgpu_dpm_is_baco_supported(struct amdgpu_device *adev) in amdgpu_dpm_is_baco_supported() argument
183 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_is_baco_supported()
184 void *pp_handle = adev->powerplay.pp_handle; in amdgpu_dpm_is_baco_supported()
199 if (adev->in_s3) in amdgpu_dpm_is_baco_supported()
202 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_is_baco_supported()
207 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_is_baco_supported()
212 int amdgpu_dpm_mode2_reset(struct amdgpu_device *adev) in amdgpu_dpm_mode2_reset() argument
214 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_mode2_reset()
215 void *pp_handle = adev->powerplay.pp_handle; in amdgpu_dpm_mode2_reset()
221 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_mode2_reset()
225 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_mode2_reset()
230 int amdgpu_dpm_enable_gfx_features(struct amdgpu_device *adev) in amdgpu_dpm_enable_gfx_features() argument
232 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_enable_gfx_features()
233 void *pp_handle = adev->powerplay.pp_handle; in amdgpu_dpm_enable_gfx_features()
239 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_enable_gfx_features()
243 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_enable_gfx_features()
248 int amdgpu_dpm_baco_reset(struct amdgpu_device *adev) in amdgpu_dpm_baco_reset() argument
250 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_baco_reset()
251 void *pp_handle = adev->powerplay.pp_handle; in amdgpu_dpm_baco_reset()
257 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_baco_reset()
268 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_baco_reset()
272 bool amdgpu_dpm_is_mode1_reset_supported(struct amdgpu_device *adev) in amdgpu_dpm_is_mode1_reset_supported() argument
274 struct smu_context *smu = adev->powerplay.pp_handle; in amdgpu_dpm_is_mode1_reset_supported()
277 if (is_support_sw_smu(adev)) { in amdgpu_dpm_is_mode1_reset_supported()
278 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_is_mode1_reset_supported()
280 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_is_mode1_reset_supported()
286 int amdgpu_dpm_mode1_reset(struct amdgpu_device *adev) in amdgpu_dpm_mode1_reset() argument
288 struct smu_context *smu = adev->powerplay.pp_handle; in amdgpu_dpm_mode1_reset()
291 if (is_support_sw_smu(adev)) { in amdgpu_dpm_mode1_reset()
292 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_mode1_reset()
294 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_mode1_reset()
300 int amdgpu_dpm_switch_power_profile(struct amdgpu_device *adev, in amdgpu_dpm_switch_power_profile() argument
304 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_switch_power_profile()
307 if (amdgpu_sriov_vf(adev)) in amdgpu_dpm_switch_power_profile()
311 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_switch_power_profile()
313 adev->powerplay.pp_handle, type, en); in amdgpu_dpm_switch_power_profile()
314 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_switch_power_profile()
320 int amdgpu_dpm_set_xgmi_pstate(struct amdgpu_device *adev, in amdgpu_dpm_set_xgmi_pstate() argument
323 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_set_xgmi_pstate()
327 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_set_xgmi_pstate()
328 ret = pp_funcs->set_xgmi_pstate(adev->powerplay.pp_handle, in amdgpu_dpm_set_xgmi_pstate()
330 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_set_xgmi_pstate()
336 int amdgpu_dpm_set_df_cstate(struct amdgpu_device *adev, in amdgpu_dpm_set_df_cstate() argument
340 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_set_df_cstate()
341 void *pp_handle = adev->powerplay.pp_handle; in amdgpu_dpm_set_df_cstate()
344 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_set_df_cstate()
346 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_set_df_cstate()
352 int amdgpu_dpm_allow_xgmi_power_down(struct amdgpu_device *adev, bool en) in amdgpu_dpm_allow_xgmi_power_down() argument
354 struct smu_context *smu = adev->powerplay.pp_handle; in amdgpu_dpm_allow_xgmi_power_down()
357 if (is_support_sw_smu(adev)) { in amdgpu_dpm_allow_xgmi_power_down()
358 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_allow_xgmi_power_down()
360 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_allow_xgmi_power_down()
366 int amdgpu_dpm_enable_mgpu_fan_boost(struct amdgpu_device *adev) in amdgpu_dpm_enable_mgpu_fan_boost() argument
368 void *pp_handle = adev->powerplay.pp_handle; in amdgpu_dpm_enable_mgpu_fan_boost()
370 adev->powerplay.pp_funcs; in amdgpu_dpm_enable_mgpu_fan_boost()
374 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_enable_mgpu_fan_boost()
376 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_enable_mgpu_fan_boost()
382 int amdgpu_dpm_set_clockgating_by_smu(struct amdgpu_device *adev, in amdgpu_dpm_set_clockgating_by_smu() argument
385 void *pp_handle = adev->powerplay.pp_handle; in amdgpu_dpm_set_clockgating_by_smu()
387 adev->powerplay.pp_funcs; in amdgpu_dpm_set_clockgating_by_smu()
391 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_set_clockgating_by_smu()
394 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_set_clockgating_by_smu()
400 int amdgpu_dpm_smu_i2c_bus_access(struct amdgpu_device *adev, in amdgpu_dpm_smu_i2c_bus_access() argument
403 void *pp_handle = adev->powerplay.pp_handle; in amdgpu_dpm_smu_i2c_bus_access()
405 adev->powerplay.pp_funcs; in amdgpu_dpm_smu_i2c_bus_access()
409 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_smu_i2c_bus_access()
412 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_smu_i2c_bus_access()
418 void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev) in amdgpu_pm_acpi_event_handler() argument
420 if (adev->pm.dpm_enabled) { in amdgpu_pm_acpi_event_handler()
421 mutex_lock(&adev->pm.mutex); in amdgpu_pm_acpi_event_handler()
423 adev->pm.ac_power = true; in amdgpu_pm_acpi_event_handler()
425 adev->pm.ac_power = false; in amdgpu_pm_acpi_event_handler()
427 if (adev->powerplay.pp_funcs && in amdgpu_pm_acpi_event_handler()
428 adev->powerplay.pp_funcs->enable_bapm) in amdgpu_pm_acpi_event_handler()
429 amdgpu_dpm_enable_bapm(adev, adev->pm.ac_power); in amdgpu_pm_acpi_event_handler()
431 if (is_support_sw_smu(adev)) in amdgpu_pm_acpi_event_handler()
432 smu_set_ac_dc(adev->powerplay.pp_handle); in amdgpu_pm_acpi_event_handler()
434 mutex_unlock(&adev->pm.mutex); in amdgpu_pm_acpi_event_handler()
438 int amdgpu_dpm_read_sensor(struct amdgpu_device *adev, enum amd_pp_sensors sensor, in amdgpu_dpm_read_sensor() argument
441 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_read_sensor()
448 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_read_sensor()
449 ret = pp_funcs->read_sensor(adev->powerplay.pp_handle, in amdgpu_dpm_read_sensor()
453 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_read_sensor()
459 void amdgpu_dpm_compute_clocks(struct amdgpu_device *adev) in amdgpu_dpm_compute_clocks() argument
461 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_compute_clocks()
464 if (!adev->pm.dpm_enabled) in amdgpu_dpm_compute_clocks()
470 if (adev->mode_info.num_crtc) in amdgpu_dpm_compute_clocks()
471 amdgpu_display_bandwidth_update(adev); in amdgpu_dpm_compute_clocks()
474 struct amdgpu_ring *ring = adev->rings[i]; in amdgpu_dpm_compute_clocks()
479 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_compute_clocks()
480 pp_funcs->pm_compute_clocks(adev->powerplay.pp_handle); in amdgpu_dpm_compute_clocks()
481 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_compute_clocks()
484 void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable) in amdgpu_dpm_enable_uvd() argument
488 if (adev->family == AMDGPU_FAMILY_SI) { in amdgpu_dpm_enable_uvd()
489 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_enable_uvd()
491 adev->pm.dpm.uvd_active = true; in amdgpu_dpm_enable_uvd()
492 adev->pm.dpm.state = POWER_STATE_TYPE_INTERNAL_UVD; in amdgpu_dpm_enable_uvd()
494 adev->pm.dpm.uvd_active = false; in amdgpu_dpm_enable_uvd()
496 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_enable_uvd()
498 amdgpu_dpm_compute_clocks(adev); in amdgpu_dpm_enable_uvd()
502 ret = amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_UVD, !enable); in amdgpu_dpm_enable_uvd()
508 void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable) in amdgpu_dpm_enable_vce() argument
512 if (adev->family == AMDGPU_FAMILY_SI) { in amdgpu_dpm_enable_vce()
513 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_enable_vce()
515 adev->pm.dpm.vce_active = true; in amdgpu_dpm_enable_vce()
517 adev->pm.dpm.vce_level = AMD_VCE_LEVEL_AC_ALL; in amdgpu_dpm_enable_vce()
519 adev->pm.dpm.vce_active = false; in amdgpu_dpm_enable_vce()
521 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_enable_vce()
523 amdgpu_dpm_compute_clocks(adev); in amdgpu_dpm_enable_vce()
527 ret = amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_VCE, !enable); in amdgpu_dpm_enable_vce()
533 void amdgpu_dpm_enable_jpeg(struct amdgpu_device *adev, bool enable) in amdgpu_dpm_enable_jpeg() argument
537 ret = amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_JPEG, !enable); in amdgpu_dpm_enable_jpeg()
543 int amdgpu_pm_load_smu_firmware(struct amdgpu_device *adev, uint32_t *smu_version) in amdgpu_pm_load_smu_firmware() argument
545 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_pm_load_smu_firmware()
551 mutex_lock(&adev->pm.mutex); in amdgpu_pm_load_smu_firmware()
552 r = pp_funcs->load_firmware(adev->powerplay.pp_handle); in amdgpu_pm_load_smu_firmware()
559 *smu_version = adev->pm.fw_version; in amdgpu_pm_load_smu_firmware()
562 mutex_unlock(&adev->pm.mutex); in amdgpu_pm_load_smu_firmware()
566 int amdgpu_dpm_handle_passthrough_sbr(struct amdgpu_device *adev, bool enable) in amdgpu_dpm_handle_passthrough_sbr() argument
570 if (is_support_sw_smu(adev)) { in amdgpu_dpm_handle_passthrough_sbr()
571 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_handle_passthrough_sbr()
572 ret = smu_handle_passthrough_sbr(adev->powerplay.pp_handle, in amdgpu_dpm_handle_passthrough_sbr()
574 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_handle_passthrough_sbr()
580 int amdgpu_dpm_send_hbm_bad_pages_num(struct amdgpu_device *adev, uint32_t size) in amdgpu_dpm_send_hbm_bad_pages_num() argument
582 struct smu_context *smu = adev->powerplay.pp_handle; in amdgpu_dpm_send_hbm_bad_pages_num()
585 if (!is_support_sw_smu(adev)) in amdgpu_dpm_send_hbm_bad_pages_num()
588 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_send_hbm_bad_pages_num()
590 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_send_hbm_bad_pages_num()
595 int amdgpu_dpm_send_hbm_bad_channel_flag(struct amdgpu_device *adev, uint32_t size) in amdgpu_dpm_send_hbm_bad_channel_flag() argument
597 struct smu_context *smu = adev->powerplay.pp_handle; in amdgpu_dpm_send_hbm_bad_channel_flag()
600 if (!is_support_sw_smu(adev)) in amdgpu_dpm_send_hbm_bad_channel_flag()
603 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_send_hbm_bad_channel_flag()
605 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_send_hbm_bad_channel_flag()
610 int amdgpu_dpm_get_dpm_freq_range(struct amdgpu_device *adev, in amdgpu_dpm_get_dpm_freq_range() argument
620 if (!is_support_sw_smu(adev)) in amdgpu_dpm_get_dpm_freq_range()
623 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_dpm_freq_range()
624 ret = smu_get_dpm_freq_range(adev->powerplay.pp_handle, in amdgpu_dpm_get_dpm_freq_range()
628 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_dpm_freq_range()
633 int amdgpu_dpm_set_soft_freq_range(struct amdgpu_device *adev, in amdgpu_dpm_set_soft_freq_range() argument
638 struct smu_context *smu = adev->powerplay.pp_handle; in amdgpu_dpm_set_soft_freq_range()
644 if (!is_support_sw_smu(adev)) in amdgpu_dpm_set_soft_freq_range()
647 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_set_soft_freq_range()
652 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_set_soft_freq_range()
657 int amdgpu_dpm_write_watermarks_table(struct amdgpu_device *adev) in amdgpu_dpm_write_watermarks_table() argument
659 struct smu_context *smu = adev->powerplay.pp_handle; in amdgpu_dpm_write_watermarks_table()
662 if (!is_support_sw_smu(adev)) in amdgpu_dpm_write_watermarks_table()
665 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_write_watermarks_table()
667 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_write_watermarks_table()
672 int amdgpu_dpm_wait_for_event(struct amdgpu_device *adev, in amdgpu_dpm_wait_for_event() argument
676 struct smu_context *smu = adev->powerplay.pp_handle; in amdgpu_dpm_wait_for_event()
679 if (!is_support_sw_smu(adev)) in amdgpu_dpm_wait_for_event()
682 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_wait_for_event()
684 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_wait_for_event()
689 int amdgpu_dpm_set_residency_gfxoff(struct amdgpu_device *adev, bool value) in amdgpu_dpm_set_residency_gfxoff() argument
691 struct smu_context *smu = adev->powerplay.pp_handle; in amdgpu_dpm_set_residency_gfxoff()
694 if (!is_support_sw_smu(adev)) in amdgpu_dpm_set_residency_gfxoff()
697 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_set_residency_gfxoff()
699 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_set_residency_gfxoff()
704 int amdgpu_dpm_get_residency_gfxoff(struct amdgpu_device *adev, u32 *value) in amdgpu_dpm_get_residency_gfxoff() argument
706 struct smu_context *smu = adev->powerplay.pp_handle; in amdgpu_dpm_get_residency_gfxoff()
709 if (!is_support_sw_smu(adev)) in amdgpu_dpm_get_residency_gfxoff()
712 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_residency_gfxoff()
714 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_residency_gfxoff()
719 int amdgpu_dpm_get_entrycount_gfxoff(struct amdgpu_device *adev, u64 *value) in amdgpu_dpm_get_entrycount_gfxoff() argument
721 struct smu_context *smu = adev->powerplay.pp_handle; in amdgpu_dpm_get_entrycount_gfxoff()
724 if (!is_support_sw_smu(adev)) in amdgpu_dpm_get_entrycount_gfxoff()
727 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_entrycount_gfxoff()
729 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_entrycount_gfxoff()
734 int amdgpu_dpm_get_status_gfxoff(struct amdgpu_device *adev, uint32_t *value) in amdgpu_dpm_get_status_gfxoff() argument
736 struct smu_context *smu = adev->powerplay.pp_handle; in amdgpu_dpm_get_status_gfxoff()
739 if (!is_support_sw_smu(adev)) in amdgpu_dpm_get_status_gfxoff()
742 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_status_gfxoff()
744 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_status_gfxoff()
749 uint64_t amdgpu_dpm_get_thermal_throttling_counter(struct amdgpu_device *adev) in amdgpu_dpm_get_thermal_throttling_counter() argument
751 struct smu_context *smu = adev->powerplay.pp_handle; in amdgpu_dpm_get_thermal_throttling_counter()
753 if (!is_support_sw_smu(adev)) in amdgpu_dpm_get_thermal_throttling_counter()
764 void amdgpu_dpm_gfx_state_change(struct amdgpu_device *adev, in amdgpu_dpm_gfx_state_change() argument
767 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_gfx_state_change()
768 if (adev->powerplay.pp_funcs && in amdgpu_dpm_gfx_state_change()
769 adev->powerplay.pp_funcs->gfx_state_change_set) in amdgpu_dpm_gfx_state_change()
770 ((adev)->powerplay.pp_funcs->gfx_state_change_set( in amdgpu_dpm_gfx_state_change()
771 (adev)->powerplay.pp_handle, state)); in amdgpu_dpm_gfx_state_change()
772 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_gfx_state_change()
775 int amdgpu_dpm_get_ecc_info(struct amdgpu_device *adev, in amdgpu_dpm_get_ecc_info() argument
778 struct smu_context *smu = adev->powerplay.pp_handle; in amdgpu_dpm_get_ecc_info()
781 if (!is_support_sw_smu(adev)) in amdgpu_dpm_get_ecc_info()
784 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_ecc_info()
786 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_ecc_info()
791 struct amd_vce_state *amdgpu_dpm_get_vce_clock_state(struct amdgpu_device *adev, in amdgpu_dpm_get_vce_clock_state() argument
794 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_get_vce_clock_state()
800 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_vce_clock_state()
801 vstate = pp_funcs->get_vce_clock_state(adev->powerplay.pp_handle, in amdgpu_dpm_get_vce_clock_state()
803 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_vce_clock_state()
808 void amdgpu_dpm_get_current_power_state(struct amdgpu_device *adev, in amdgpu_dpm_get_current_power_state() argument
811 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_get_current_power_state()
813 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_current_power_state()
816 *state = adev->pm.dpm.user_state; in amdgpu_dpm_get_current_power_state()
820 *state = pp_funcs->get_current_power_state(adev->powerplay.pp_handle); in amdgpu_dpm_get_current_power_state()
823 *state = adev->pm.dpm.user_state; in amdgpu_dpm_get_current_power_state()
826 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_current_power_state()
829 void amdgpu_dpm_set_power_state(struct amdgpu_device *adev, in amdgpu_dpm_set_power_state() argument
832 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_set_power_state()
833 adev->pm.dpm.user_state = state; in amdgpu_dpm_set_power_state()
834 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_set_power_state()
836 if (is_support_sw_smu(adev)) in amdgpu_dpm_set_power_state()
839 if (amdgpu_dpm_dispatch_task(adev, in amdgpu_dpm_set_power_state()
842 amdgpu_dpm_compute_clocks(adev); in amdgpu_dpm_set_power_state()
845 enum amd_dpm_forced_level amdgpu_dpm_get_performance_level(struct amdgpu_device *adev) in amdgpu_dpm_get_performance_level() argument
847 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_get_performance_level()
853 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_performance_level()
855 level = pp_funcs->get_performance_level(adev->powerplay.pp_handle); in amdgpu_dpm_get_performance_level()
857 level = adev->pm.dpm.forced_level; in amdgpu_dpm_get_performance_level()
858 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_performance_level()
863 int amdgpu_dpm_force_performance_level(struct amdgpu_device *adev, in amdgpu_dpm_force_performance_level() argument
866 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_force_performance_level()
876 if (adev->pm.dpm.thermal_active) in amdgpu_dpm_force_performance_level()
879 current_level = amdgpu_dpm_get_performance_level(adev); in amdgpu_dpm_force_performance_level()
883 if (adev->asic_type == CHIP_RAVEN) { in amdgpu_dpm_force_performance_level()
884 if (!(adev->apu_flags & AMD_APU_IS_RAVEN2)) { in amdgpu_dpm_force_performance_level()
887 amdgpu_gfx_off_ctrl(adev, false); in amdgpu_dpm_force_performance_level()
890 amdgpu_gfx_off_ctrl(adev, true); in amdgpu_dpm_force_performance_level()
901 amdgpu_device_ip_set_powergating_state(adev, in amdgpu_dpm_force_performance_level()
904 amdgpu_device_ip_set_clockgating_state(adev, in amdgpu_dpm_force_performance_level()
910 amdgpu_device_ip_set_clockgating_state(adev, in amdgpu_dpm_force_performance_level()
913 amdgpu_device_ip_set_powergating_state(adev, in amdgpu_dpm_force_performance_level()
918 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_force_performance_level()
920 if (pp_funcs->force_performance_level(adev->powerplay.pp_handle, in amdgpu_dpm_force_performance_level()
922 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_force_performance_level()
926 adev->pm.dpm.forced_level = level; in amdgpu_dpm_force_performance_level()
928 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_force_performance_level()
933 int amdgpu_dpm_get_pp_num_states(struct amdgpu_device *adev, in amdgpu_dpm_get_pp_num_states() argument
936 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_get_pp_num_states()
942 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_pp_num_states()
943 ret = pp_funcs->get_pp_num_states(adev->powerplay.pp_handle, in amdgpu_dpm_get_pp_num_states()
945 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_pp_num_states()
950 int amdgpu_dpm_dispatch_task(struct amdgpu_device *adev, in amdgpu_dpm_dispatch_task() argument
954 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_dispatch_task()
960 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_dispatch_task()
961 ret = pp_funcs->dispatch_tasks(adev->powerplay.pp_handle, in amdgpu_dpm_dispatch_task()
964 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_dispatch_task()
969 int amdgpu_dpm_get_pp_table(struct amdgpu_device *adev, char **table) in amdgpu_dpm_get_pp_table() argument
971 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_get_pp_table()
977 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_pp_table()
978 ret = pp_funcs->get_pp_table(adev->powerplay.pp_handle, in amdgpu_dpm_get_pp_table()
980 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_pp_table()
985 int amdgpu_dpm_set_fine_grain_clk_vol(struct amdgpu_device *adev, in amdgpu_dpm_set_fine_grain_clk_vol() argument
990 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_set_fine_grain_clk_vol()
996 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_set_fine_grain_clk_vol()
997 ret = pp_funcs->set_fine_grain_clk_vol(adev->powerplay.pp_handle, in amdgpu_dpm_set_fine_grain_clk_vol()
1001 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_set_fine_grain_clk_vol()
1006 int amdgpu_dpm_odn_edit_dpm_table(struct amdgpu_device *adev, in amdgpu_dpm_odn_edit_dpm_table() argument
1011 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_odn_edit_dpm_table()
1017 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_odn_edit_dpm_table()
1018 ret = pp_funcs->odn_edit_dpm_table(adev->powerplay.pp_handle, in amdgpu_dpm_odn_edit_dpm_table()
1022 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_odn_edit_dpm_table()
1027 int amdgpu_dpm_print_clock_levels(struct amdgpu_device *adev, in amdgpu_dpm_print_clock_levels() argument
1031 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_print_clock_levels()
1037 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_print_clock_levels()
1038 ret = pp_funcs->print_clock_levels(adev->powerplay.pp_handle, in amdgpu_dpm_print_clock_levels()
1041 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_print_clock_levels()
1046 int amdgpu_dpm_emit_clock_levels(struct amdgpu_device *adev, in amdgpu_dpm_emit_clock_levels() argument
1051 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_emit_clock_levels()
1057 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_emit_clock_levels()
1058 ret = pp_funcs->emit_clock_levels(adev->powerplay.pp_handle, in amdgpu_dpm_emit_clock_levels()
1062 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_emit_clock_levels()
1067 int amdgpu_dpm_set_ppfeature_status(struct amdgpu_device *adev, in amdgpu_dpm_set_ppfeature_status() argument
1070 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_set_ppfeature_status()
1076 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_set_ppfeature_status()
1077 ret = pp_funcs->set_ppfeature_status(adev->powerplay.pp_handle, in amdgpu_dpm_set_ppfeature_status()
1079 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_set_ppfeature_status()
1084 int amdgpu_dpm_get_ppfeature_status(struct amdgpu_device *adev, char *buf) in amdgpu_dpm_get_ppfeature_status() argument
1086 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_get_ppfeature_status()
1092 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_ppfeature_status()
1093 ret = pp_funcs->get_ppfeature_status(adev->powerplay.pp_handle, in amdgpu_dpm_get_ppfeature_status()
1095 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_ppfeature_status()
1100 int amdgpu_dpm_force_clock_level(struct amdgpu_device *adev, in amdgpu_dpm_force_clock_level() argument
1104 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_force_clock_level()
1110 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_force_clock_level()
1111 ret = pp_funcs->force_clock_level(adev->powerplay.pp_handle, in amdgpu_dpm_force_clock_level()
1114 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_force_clock_level()
1119 int amdgpu_dpm_get_sclk_od(struct amdgpu_device *adev) in amdgpu_dpm_get_sclk_od() argument
1121 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_get_sclk_od()
1127 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_sclk_od()
1128 ret = pp_funcs->get_sclk_od(adev->powerplay.pp_handle); in amdgpu_dpm_get_sclk_od()
1129 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_sclk_od()
1134 int amdgpu_dpm_set_sclk_od(struct amdgpu_device *adev, uint32_t value) in amdgpu_dpm_set_sclk_od() argument
1136 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_set_sclk_od()
1138 if (is_support_sw_smu(adev)) in amdgpu_dpm_set_sclk_od()
1141 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_set_sclk_od()
1143 pp_funcs->set_sclk_od(adev->powerplay.pp_handle, value); in amdgpu_dpm_set_sclk_od()
1144 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_set_sclk_od()
1146 if (amdgpu_dpm_dispatch_task(adev, in amdgpu_dpm_set_sclk_od()
1149 adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps; in amdgpu_dpm_set_sclk_od()
1150 amdgpu_dpm_compute_clocks(adev); in amdgpu_dpm_set_sclk_od()
1156 int amdgpu_dpm_get_mclk_od(struct amdgpu_device *adev) in amdgpu_dpm_get_mclk_od() argument
1158 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_get_mclk_od()
1164 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_mclk_od()
1165 ret = pp_funcs->get_mclk_od(adev->powerplay.pp_handle); in amdgpu_dpm_get_mclk_od()
1166 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_mclk_od()
1171 int amdgpu_dpm_set_mclk_od(struct amdgpu_device *adev, uint32_t value) in amdgpu_dpm_set_mclk_od() argument
1173 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_set_mclk_od()
1175 if (is_support_sw_smu(adev)) in amdgpu_dpm_set_mclk_od()
1178 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_set_mclk_od()
1180 pp_funcs->set_mclk_od(adev->powerplay.pp_handle, value); in amdgpu_dpm_set_mclk_od()
1181 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_set_mclk_od()
1183 if (amdgpu_dpm_dispatch_task(adev, in amdgpu_dpm_set_mclk_od()
1186 adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps; in amdgpu_dpm_set_mclk_od()
1187 amdgpu_dpm_compute_clocks(adev); in amdgpu_dpm_set_mclk_od()
1193 int amdgpu_dpm_get_power_profile_mode(struct amdgpu_device *adev, in amdgpu_dpm_get_power_profile_mode() argument
1196 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_get_power_profile_mode()
1202 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_power_profile_mode()
1203 ret = pp_funcs->get_power_profile_mode(adev->powerplay.pp_handle, in amdgpu_dpm_get_power_profile_mode()
1205 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_power_profile_mode()
1210 int amdgpu_dpm_set_power_profile_mode(struct amdgpu_device *adev, in amdgpu_dpm_set_power_profile_mode() argument
1213 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_set_power_profile_mode()
1219 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_set_power_profile_mode()
1220 ret = pp_funcs->set_power_profile_mode(adev->powerplay.pp_handle, in amdgpu_dpm_set_power_profile_mode()
1223 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_set_power_profile_mode()
1228 int amdgpu_dpm_get_gpu_metrics(struct amdgpu_device *adev, void **table) in amdgpu_dpm_get_gpu_metrics() argument
1230 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_get_gpu_metrics()
1236 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_gpu_metrics()
1237 ret = pp_funcs->get_gpu_metrics(adev->powerplay.pp_handle, in amdgpu_dpm_get_gpu_metrics()
1239 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_gpu_metrics()
1244 int amdgpu_dpm_get_fan_control_mode(struct amdgpu_device *adev, in amdgpu_dpm_get_fan_control_mode() argument
1247 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_get_fan_control_mode()
1253 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_fan_control_mode()
1254 ret = pp_funcs->get_fan_control_mode(adev->powerplay.pp_handle, in amdgpu_dpm_get_fan_control_mode()
1256 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_fan_control_mode()
1261 int amdgpu_dpm_set_fan_speed_pwm(struct amdgpu_device *adev, in amdgpu_dpm_set_fan_speed_pwm() argument
1264 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_set_fan_speed_pwm()
1270 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_set_fan_speed_pwm()
1271 ret = pp_funcs->set_fan_speed_pwm(adev->powerplay.pp_handle, in amdgpu_dpm_set_fan_speed_pwm()
1273 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_set_fan_speed_pwm()
1278 int amdgpu_dpm_get_fan_speed_pwm(struct amdgpu_device *adev, in amdgpu_dpm_get_fan_speed_pwm() argument
1281 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_get_fan_speed_pwm()
1287 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_fan_speed_pwm()
1288 ret = pp_funcs->get_fan_speed_pwm(adev->powerplay.pp_handle, in amdgpu_dpm_get_fan_speed_pwm()
1290 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_fan_speed_pwm()
1295 int amdgpu_dpm_get_fan_speed_rpm(struct amdgpu_device *adev, in amdgpu_dpm_get_fan_speed_rpm() argument
1298 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_get_fan_speed_rpm()
1304 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_fan_speed_rpm()
1305 ret = pp_funcs->get_fan_speed_rpm(adev->powerplay.pp_handle, in amdgpu_dpm_get_fan_speed_rpm()
1307 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_fan_speed_rpm()
1312 int amdgpu_dpm_set_fan_speed_rpm(struct amdgpu_device *adev, in amdgpu_dpm_set_fan_speed_rpm() argument
1315 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_set_fan_speed_rpm()
1321 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_set_fan_speed_rpm()
1322 ret = pp_funcs->set_fan_speed_rpm(adev->powerplay.pp_handle, in amdgpu_dpm_set_fan_speed_rpm()
1324 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_set_fan_speed_rpm()
1329 int amdgpu_dpm_set_fan_control_mode(struct amdgpu_device *adev, in amdgpu_dpm_set_fan_control_mode() argument
1332 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_set_fan_control_mode()
1338 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_set_fan_control_mode()
1339 ret = pp_funcs->set_fan_control_mode(adev->powerplay.pp_handle, in amdgpu_dpm_set_fan_control_mode()
1341 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_set_fan_control_mode()
1346 int amdgpu_dpm_get_power_limit(struct amdgpu_device *adev, in amdgpu_dpm_get_power_limit() argument
1351 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_get_power_limit()
1357 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_power_limit()
1358 ret = pp_funcs->get_power_limit(adev->powerplay.pp_handle, in amdgpu_dpm_get_power_limit()
1362 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_power_limit()
1367 int amdgpu_dpm_set_power_limit(struct amdgpu_device *adev, in amdgpu_dpm_set_power_limit() argument
1370 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_set_power_limit()
1376 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_set_power_limit()
1377 ret = pp_funcs->set_power_limit(adev->powerplay.pp_handle, in amdgpu_dpm_set_power_limit()
1379 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_set_power_limit()
1384 int amdgpu_dpm_is_cclk_dpm_supported(struct amdgpu_device *adev) in amdgpu_dpm_is_cclk_dpm_supported() argument
1388 if (!is_support_sw_smu(adev)) in amdgpu_dpm_is_cclk_dpm_supported()
1391 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_is_cclk_dpm_supported()
1392 cclk_dpm_supported = is_support_cclk_dpm(adev); in amdgpu_dpm_is_cclk_dpm_supported()
1393 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_is_cclk_dpm_supported()
1398 int amdgpu_dpm_debugfs_print_current_performance_level(struct amdgpu_device *adev, in amdgpu_dpm_debugfs_print_current_performance_level() argument
1401 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_debugfs_print_current_performance_level()
1406 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_debugfs_print_current_performance_level()
1407 pp_funcs->debugfs_print_current_performance_level(adev->powerplay.pp_handle, in amdgpu_dpm_debugfs_print_current_performance_level()
1409 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_debugfs_print_current_performance_level()
1414 int amdgpu_dpm_get_smu_prv_buf_details(struct amdgpu_device *adev, in amdgpu_dpm_get_smu_prv_buf_details() argument
1418 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_get_smu_prv_buf_details()
1424 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_smu_prv_buf_details()
1425 ret = pp_funcs->get_smu_prv_buf_details(adev->powerplay.pp_handle, in amdgpu_dpm_get_smu_prv_buf_details()
1428 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_smu_prv_buf_details()
1433 int amdgpu_dpm_is_overdrive_supported(struct amdgpu_device *adev) in amdgpu_dpm_is_overdrive_supported() argument
1435 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle; in amdgpu_dpm_is_overdrive_supported()
1436 struct smu_context *smu = adev->powerplay.pp_handle; in amdgpu_dpm_is_overdrive_supported()
1438 if ((is_support_sw_smu(adev) && smu->od_enabled) || in amdgpu_dpm_is_overdrive_supported()
1439 (is_support_sw_smu(adev) && smu->is_apu) || in amdgpu_dpm_is_overdrive_supported()
1440 (!is_support_sw_smu(adev) && hwmgr->od_enabled)) in amdgpu_dpm_is_overdrive_supported()
1446 int amdgpu_dpm_set_pp_table(struct amdgpu_device *adev, in amdgpu_dpm_set_pp_table() argument
1450 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_set_pp_table()
1456 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_set_pp_table()
1457 ret = pp_funcs->set_pp_table(adev->powerplay.pp_handle, in amdgpu_dpm_set_pp_table()
1460 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_set_pp_table()
1465 int amdgpu_dpm_get_num_cpu_cores(struct amdgpu_device *adev) in amdgpu_dpm_get_num_cpu_cores() argument
1467 struct smu_context *smu = adev->powerplay.pp_handle; in amdgpu_dpm_get_num_cpu_cores()
1469 if (!is_support_sw_smu(adev)) in amdgpu_dpm_get_num_cpu_cores()
1475 void amdgpu_dpm_stb_debug_fs_init(struct amdgpu_device *adev) in amdgpu_dpm_stb_debug_fs_init() argument
1477 if (!is_support_sw_smu(adev)) in amdgpu_dpm_stb_debug_fs_init()
1480 amdgpu_smu_stb_debug_fs_init(adev); in amdgpu_dpm_stb_debug_fs_init()
1483 int amdgpu_dpm_display_configuration_change(struct amdgpu_device *adev, in amdgpu_dpm_display_configuration_change() argument
1486 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_display_configuration_change()
1492 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_display_configuration_change()
1493 ret = pp_funcs->display_configuration_change(adev->powerplay.pp_handle, in amdgpu_dpm_display_configuration_change()
1495 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_display_configuration_change()
1500 int amdgpu_dpm_get_clock_by_type(struct amdgpu_device *adev, in amdgpu_dpm_get_clock_by_type() argument
1504 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_get_clock_by_type()
1510 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_clock_by_type()
1511 ret = pp_funcs->get_clock_by_type(adev->powerplay.pp_handle, in amdgpu_dpm_get_clock_by_type()
1514 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_clock_by_type()
1519 int amdgpu_dpm_get_display_mode_validation_clks(struct amdgpu_device *adev, in amdgpu_dpm_get_display_mode_validation_clks() argument
1522 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_get_display_mode_validation_clks()
1528 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_display_mode_validation_clks()
1529 ret = pp_funcs->get_display_mode_validation_clocks(adev->powerplay.pp_handle, in amdgpu_dpm_get_display_mode_validation_clks()
1531 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_display_mode_validation_clks()
1536 int amdgpu_dpm_get_clock_by_type_with_latency(struct amdgpu_device *adev, in amdgpu_dpm_get_clock_by_type_with_latency() argument
1540 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_get_clock_by_type_with_latency()
1546 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_clock_by_type_with_latency()
1547 ret = pp_funcs->get_clock_by_type_with_latency(adev->powerplay.pp_handle, in amdgpu_dpm_get_clock_by_type_with_latency()
1550 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_clock_by_type_with_latency()
1555 int amdgpu_dpm_get_clock_by_type_with_voltage(struct amdgpu_device *adev, in amdgpu_dpm_get_clock_by_type_with_voltage() argument
1559 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_get_clock_by_type_with_voltage()
1565 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_clock_by_type_with_voltage()
1566 ret = pp_funcs->get_clock_by_type_with_voltage(adev->powerplay.pp_handle, in amdgpu_dpm_get_clock_by_type_with_voltage()
1569 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_clock_by_type_with_voltage()
1574 int amdgpu_dpm_set_watermarks_for_clocks_ranges(struct amdgpu_device *adev, in amdgpu_dpm_set_watermarks_for_clocks_ranges() argument
1577 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_set_watermarks_for_clocks_ranges()
1583 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_set_watermarks_for_clocks_ranges()
1584 ret = pp_funcs->set_watermarks_for_clocks_ranges(adev->powerplay.pp_handle, in amdgpu_dpm_set_watermarks_for_clocks_ranges()
1586 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_set_watermarks_for_clocks_ranges()
1591 int amdgpu_dpm_display_clock_voltage_request(struct amdgpu_device *adev, in amdgpu_dpm_display_clock_voltage_request() argument
1594 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_display_clock_voltage_request()
1600 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_display_clock_voltage_request()
1601 ret = pp_funcs->display_clock_voltage_request(adev->powerplay.pp_handle, in amdgpu_dpm_display_clock_voltage_request()
1603 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_display_clock_voltage_request()
1608 int amdgpu_dpm_get_current_clocks(struct amdgpu_device *adev, in amdgpu_dpm_get_current_clocks() argument
1611 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_get_current_clocks()
1617 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_current_clocks()
1618 ret = pp_funcs->get_current_clocks(adev->powerplay.pp_handle, in amdgpu_dpm_get_current_clocks()
1620 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_current_clocks()
1625 void amdgpu_dpm_notify_smu_enable_pwe(struct amdgpu_device *adev) in amdgpu_dpm_notify_smu_enable_pwe() argument
1627 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_notify_smu_enable_pwe()
1632 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_notify_smu_enable_pwe()
1633 pp_funcs->notify_smu_enable_pwe(adev->powerplay.pp_handle); in amdgpu_dpm_notify_smu_enable_pwe()
1634 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_notify_smu_enable_pwe()
1637 int amdgpu_dpm_set_active_display_count(struct amdgpu_device *adev, in amdgpu_dpm_set_active_display_count() argument
1640 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_set_active_display_count()
1646 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_set_active_display_count()
1647 ret = pp_funcs->set_active_display_count(adev->powerplay.pp_handle, in amdgpu_dpm_set_active_display_count()
1649 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_set_active_display_count()
1654 int amdgpu_dpm_set_min_deep_sleep_dcefclk(struct amdgpu_device *adev, in amdgpu_dpm_set_min_deep_sleep_dcefclk() argument
1657 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_set_min_deep_sleep_dcefclk()
1663 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_set_min_deep_sleep_dcefclk()
1664 ret = pp_funcs->set_min_deep_sleep_dcefclk(adev->powerplay.pp_handle, in amdgpu_dpm_set_min_deep_sleep_dcefclk()
1666 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_set_min_deep_sleep_dcefclk()
1671 void amdgpu_dpm_set_hard_min_dcefclk_by_freq(struct amdgpu_device *adev, in amdgpu_dpm_set_hard_min_dcefclk_by_freq() argument
1674 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_set_hard_min_dcefclk_by_freq()
1679 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_set_hard_min_dcefclk_by_freq()
1680 pp_funcs->set_hard_min_dcefclk_by_freq(adev->powerplay.pp_handle, in amdgpu_dpm_set_hard_min_dcefclk_by_freq()
1682 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_set_hard_min_dcefclk_by_freq()
1685 void amdgpu_dpm_set_hard_min_fclk_by_freq(struct amdgpu_device *adev, in amdgpu_dpm_set_hard_min_fclk_by_freq() argument
1688 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_set_hard_min_fclk_by_freq()
1693 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_set_hard_min_fclk_by_freq()
1694 pp_funcs->set_hard_min_fclk_by_freq(adev->powerplay.pp_handle, in amdgpu_dpm_set_hard_min_fclk_by_freq()
1696 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_set_hard_min_fclk_by_freq()
1699 int amdgpu_dpm_display_disable_memory_clock_switch(struct amdgpu_device *adev, in amdgpu_dpm_display_disable_memory_clock_switch() argument
1702 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_display_disable_memory_clock_switch()
1708 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_display_disable_memory_clock_switch()
1709 ret = pp_funcs->display_disable_memory_clock_switch(adev->powerplay.pp_handle, in amdgpu_dpm_display_disable_memory_clock_switch()
1711 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_display_disable_memory_clock_switch()
1716 int amdgpu_dpm_get_max_sustainable_clocks_by_dc(struct amdgpu_device *adev, in amdgpu_dpm_get_max_sustainable_clocks_by_dc() argument
1719 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_get_max_sustainable_clocks_by_dc()
1725 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_max_sustainable_clocks_by_dc()
1726 ret = pp_funcs->get_max_sustainable_clocks_by_dc(adev->powerplay.pp_handle, in amdgpu_dpm_get_max_sustainable_clocks_by_dc()
1728 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_max_sustainable_clocks_by_dc()
1733 enum pp_smu_status amdgpu_dpm_get_uclk_dpm_states(struct amdgpu_device *adev, in amdgpu_dpm_get_uclk_dpm_states() argument
1737 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_get_uclk_dpm_states()
1743 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_uclk_dpm_states()
1744 ret = pp_funcs->get_uclk_dpm_states(adev->powerplay.pp_handle, in amdgpu_dpm_get_uclk_dpm_states()
1747 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_uclk_dpm_states()
1752 int amdgpu_dpm_get_dpm_clock_table(struct amdgpu_device *adev, in amdgpu_dpm_get_dpm_clock_table() argument
1755 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_get_dpm_clock_table()
1761 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_dpm_clock_table()
1762 ret = pp_funcs->get_dpm_clock_table(adev->powerplay.pp_handle, in amdgpu_dpm_get_dpm_clock_table()
1764 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_dpm_clock_table()