Lines Matching refs:dpm
127 if (rps == adev->pm.dpm.current_ps) in amdgpu_dpm_print_ps_status()
129 if (rps == adev->pm.dpm.requested_ps) in amdgpu_dpm_print_ps_status()
131 if (rps == adev->pm.dpm.boot_ps) in amdgpu_dpm_print_ps_status()
143 for (i = 0; i < adev->pm.dpm.num_ps; i++) in amdgpu_pm_print_power_states()
144 amdgpu_dpm_print_power_state(adev, &adev->pm.dpm.ps[i]); in amdgpu_pm_print_power_states()
172 adev->pm.dpm.platform_caps = le32_to_cpu(power_info->pplib.ulPlatformCaps); in amdgpu_get_platform_caps()
173 adev->pm.dpm.backbias_response_time = le16_to_cpu(power_info->pplib.usBackbiasTime); in amdgpu_get_platform_caps()
174 adev->pm.dpm.voltage_response_time = le16_to_cpu(power_info->pplib.usVoltageTime); in amdgpu_get_platform_caps()
242 adev->pm.dpm.fan.t_hyst = fan_info->fan.ucTHyst; in amdgpu_parse_extended_power_table()
243 adev->pm.dpm.fan.t_min = le16_to_cpu(fan_info->fan.usTMin); in amdgpu_parse_extended_power_table()
244 adev->pm.dpm.fan.t_med = le16_to_cpu(fan_info->fan.usTMed); in amdgpu_parse_extended_power_table()
245 adev->pm.dpm.fan.t_high = le16_to_cpu(fan_info->fan.usTHigh); in amdgpu_parse_extended_power_table()
246 adev->pm.dpm.fan.pwm_min = le16_to_cpu(fan_info->fan.usPWMMin); in amdgpu_parse_extended_power_table()
247 adev->pm.dpm.fan.pwm_med = le16_to_cpu(fan_info->fan.usPWMMed); in amdgpu_parse_extended_power_table()
248 adev->pm.dpm.fan.pwm_high = le16_to_cpu(fan_info->fan.usPWMHigh); in amdgpu_parse_extended_power_table()
250 adev->pm.dpm.fan.t_max = le16_to_cpu(fan_info->fan2.usTMax); in amdgpu_parse_extended_power_table()
252 adev->pm.dpm.fan.t_max = 10900; in amdgpu_parse_extended_power_table()
253 adev->pm.dpm.fan.cycle_delay = 100000; in amdgpu_parse_extended_power_table()
255 adev->pm.dpm.fan.control_mode = fan_info->fan3.ucFanControlMode; in amdgpu_parse_extended_power_table()
256 adev->pm.dpm.fan.default_max_fan_pwm = in amdgpu_parse_extended_power_table()
258 adev->pm.dpm.fan.default_fan_output_sensitivity = 4836; in amdgpu_parse_extended_power_table()
259 adev->pm.dpm.fan.fan_output_sensitivity = in amdgpu_parse_extended_power_table()
262 adev->pm.dpm.fan.ucode_fan_control = true; in amdgpu_parse_extended_power_table()
273 ret = amdgpu_parse_clk_voltage_dep_table(&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk, in amdgpu_parse_extended_power_table()
284 ret = amdgpu_parse_clk_voltage_dep_table(&adev->pm.dpm.dyn_state.vddci_dependency_on_mclk, in amdgpu_parse_extended_power_table()
295 ret = amdgpu_parse_clk_voltage_dep_table(&adev->pm.dpm.dyn_state.vddc_dependency_on_mclk, in amdgpu_parse_extended_power_table()
306 ret = amdgpu_parse_clk_voltage_dep_table(&adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk, in amdgpu_parse_extended_power_table()
319 adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk = in amdgpu_parse_extended_power_table()
322 adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk = in amdgpu_parse_extended_power_table()
325 adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc = in amdgpu_parse_extended_power_table()
327 adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddci = in amdgpu_parse_extended_power_table()
338 adev->pm.dpm.dyn_state.phase_shedding_limits_table.entries = in amdgpu_parse_extended_power_table()
342 if (!adev->pm.dpm.dyn_state.phase_shedding_limits_table.entries) { in amdgpu_parse_extended_power_table()
349 adev->pm.dpm.dyn_state.phase_shedding_limits_table.entries[i].sclk = in amdgpu_parse_extended_power_table()
351 adev->pm.dpm.dyn_state.phase_shedding_limits_table.entries[i].mclk = in amdgpu_parse_extended_power_table()
353 adev->pm.dpm.dyn_state.phase_shedding_limits_table.entries[i].voltage = in amdgpu_parse_extended_power_table()
358 adev->pm.dpm.dyn_state.phase_shedding_limits_table.count = in amdgpu_parse_extended_power_table()
366 adev->pm.dpm.tdp_limit = le32_to_cpu(power_info->pplib5.ulTDPLimit); in amdgpu_parse_extended_power_table()
367 adev->pm.dpm.near_tdp_limit = le32_to_cpu(power_info->pplib5.ulNearTDPLimit); in amdgpu_parse_extended_power_table()
368 adev->pm.dpm.near_tdp_limit_adjusted = adev->pm.dpm.near_tdp_limit; in amdgpu_parse_extended_power_table()
369 adev->pm.dpm.tdp_od_limit = le16_to_cpu(power_info->pplib5.usTDPODLimit); in amdgpu_parse_extended_power_table()
370 if (adev->pm.dpm.tdp_od_limit) in amdgpu_parse_extended_power_table()
371 adev->pm.dpm.power_control = true; in amdgpu_parse_extended_power_table()
373 adev->pm.dpm.power_control = false; in amdgpu_parse_extended_power_table()
374 adev->pm.dpm.tdp_adjustment = 0; in amdgpu_parse_extended_power_table()
375 adev->pm.dpm.sq_ramping_threshold = le32_to_cpu(power_info->pplib5.ulSQRampingThreshold); in amdgpu_parse_extended_power_table()
376 adev->pm.dpm.cac_leakage = le32_to_cpu(power_info->pplib5.ulCACLeakage); in amdgpu_parse_extended_power_table()
377 adev->pm.dpm.load_line_slope = le16_to_cpu(power_info->pplib5.usLoadLineSlope); in amdgpu_parse_extended_power_table()
385 adev->pm.dpm.dyn_state.cac_leakage_table.entries = kzalloc(size, GFP_KERNEL); in amdgpu_parse_extended_power_table()
386 if (!adev->pm.dpm.dyn_state.cac_leakage_table.entries) { in amdgpu_parse_extended_power_table()
392 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) { in amdgpu_parse_extended_power_table()
393 adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc1 = in amdgpu_parse_extended_power_table()
395 adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc2 = in amdgpu_parse_extended_power_table()
397 adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc3 = in amdgpu_parse_extended_power_table()
400 adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc = in amdgpu_parse_extended_power_table()
402 adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].leakage = in amdgpu_parse_extended_power_table()
408 adev->pm.dpm.dyn_state.cac_leakage_table.count = cac_table->ucNumEntries; in amdgpu_parse_extended_power_table()
439 adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries = in amdgpu_parse_extended_power_table()
441 if (!adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries) { in amdgpu_parse_extended_power_table()
445 adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count = in amdgpu_parse_extended_power_table()
453 adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].evclk = in amdgpu_parse_extended_power_table()
455 adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].ecclk = in amdgpu_parse_extended_power_table()
457 adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].v = in amdgpu_parse_extended_power_table()
462 adev->pm.dpm.num_of_vce_states = in amdgpu_parse_extended_power_table()
465 for (i = 0; i < adev->pm.dpm.num_of_vce_states; i++) { in amdgpu_parse_extended_power_table()
469 adev->pm.dpm.vce_states[i].evclk = in amdgpu_parse_extended_power_table()
471 adev->pm.dpm.vce_states[i].ecclk = in amdgpu_parse_extended_power_table()
473 adev->pm.dpm.vce_states[i].clk_idx = in amdgpu_parse_extended_power_table()
475 adev->pm.dpm.vce_states[i].pstate = in amdgpu_parse_extended_power_table()
494 adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries = in amdgpu_parse_extended_power_table()
496 if (!adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries) { in amdgpu_parse_extended_power_table()
500 adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count = in amdgpu_parse_extended_power_table()
507 adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].vclk = in amdgpu_parse_extended_power_table()
509 adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].dclk = in amdgpu_parse_extended_power_table()
511 adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].v = in amdgpu_parse_extended_power_table()
526 adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries = in amdgpu_parse_extended_power_table()
528 if (!adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries) { in amdgpu_parse_extended_power_table()
532 adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count = in amdgpu_parse_extended_power_table()
536 adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[i].clk = in amdgpu_parse_extended_power_table()
538 adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[i].v = in amdgpu_parse_extended_power_table()
549 adev->pm.dpm.dyn_state.ppm_table = in amdgpu_parse_extended_power_table()
551 if (!adev->pm.dpm.dyn_state.ppm_table) { in amdgpu_parse_extended_power_table()
555 adev->pm.dpm.dyn_state.ppm_table->ppm_design = ppm->ucPpmDesign; in amdgpu_parse_extended_power_table()
556 adev->pm.dpm.dyn_state.ppm_table->cpu_core_number = in amdgpu_parse_extended_power_table()
558 adev->pm.dpm.dyn_state.ppm_table->platform_tdp = in amdgpu_parse_extended_power_table()
560 adev->pm.dpm.dyn_state.ppm_table->small_ac_platform_tdp = in amdgpu_parse_extended_power_table()
562 adev->pm.dpm.dyn_state.ppm_table->platform_tdc = in amdgpu_parse_extended_power_table()
564 adev->pm.dpm.dyn_state.ppm_table->small_ac_platform_tdc = in amdgpu_parse_extended_power_table()
566 adev->pm.dpm.dyn_state.ppm_table->apu_tdp = in amdgpu_parse_extended_power_table()
568 adev->pm.dpm.dyn_state.ppm_table->dgpu_tdp = in amdgpu_parse_extended_power_table()
570 adev->pm.dpm.dyn_state.ppm_table->dgpu_ulv_power = in amdgpu_parse_extended_power_table()
572 adev->pm.dpm.dyn_state.ppm_table->tj_max = in amdgpu_parse_extended_power_table()
584 adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries = in amdgpu_parse_extended_power_table()
586 if (!adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries) { in amdgpu_parse_extended_power_table()
590 adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count = in amdgpu_parse_extended_power_table()
594 adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[i].clk = in amdgpu_parse_extended_power_table()
596 adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[i].v = in amdgpu_parse_extended_power_table()
607 adev->pm.dpm.dyn_state.cac_tdp_table = in amdgpu_parse_extended_power_table()
609 if (!adev->pm.dpm.dyn_state.cac_tdp_table) { in amdgpu_parse_extended_power_table()
617 adev->pm.dpm.dyn_state.cac_tdp_table->maximum_power_delivery_limit = in amdgpu_parse_extended_power_table()
624 adev->pm.dpm.dyn_state.cac_tdp_table->maximum_power_delivery_limit = 255; in amdgpu_parse_extended_power_table()
627 adev->pm.dpm.dyn_state.cac_tdp_table->tdp = le16_to_cpu(pt->usTDP); in amdgpu_parse_extended_power_table()
628 adev->pm.dpm.dyn_state.cac_tdp_table->configurable_tdp = in amdgpu_parse_extended_power_table()
630 adev->pm.dpm.dyn_state.cac_tdp_table->tdc = le16_to_cpu(pt->usTDC); in amdgpu_parse_extended_power_table()
631 adev->pm.dpm.dyn_state.cac_tdp_table->battery_power_limit = in amdgpu_parse_extended_power_table()
633 adev->pm.dpm.dyn_state.cac_tdp_table->small_power_limit = in amdgpu_parse_extended_power_table()
635 adev->pm.dpm.dyn_state.cac_tdp_table->low_cac_leakage = in amdgpu_parse_extended_power_table()
637 adev->pm.dpm.dyn_state.cac_tdp_table->high_cac_leakage = in amdgpu_parse_extended_power_table()
646 &adev->pm.dpm.dyn_state.vddgfx_dependency_on_sclk, in amdgpu_parse_extended_power_table()
649 kfree(adev->pm.dpm.dyn_state.vddgfx_dependency_on_sclk.entries); in amdgpu_parse_extended_power_table()
660 struct amdgpu_dpm_dynamic_state *dyn_state = &adev->pm.dpm.dyn_state; in amdgpu_free_extended_power_table()
814 if (idx < adev->pm.dpm.num_of_vce_states) in amdgpu_get_vce_clock_state()
815 return &adev->pm.dpm.vce_states[idx]; in amdgpu_get_vce_clock_state()
826 bool single_display = (adev->pm.dpm.new_active_crtc_count < 2) ? in amdgpu_dpm_pick_power_state()
846 for (i = 0; i < adev->pm.dpm.num_ps; i++) { in amdgpu_dpm_pick_power_state()
847 ps = &adev->pm.dpm.ps[i]; in amdgpu_dpm_pick_power_state()
880 if (adev->pm.dpm.uvd_ps) in amdgpu_dpm_pick_power_state()
881 return adev->pm.dpm.uvd_ps; in amdgpu_dpm_pick_power_state()
901 return adev->pm.dpm.boot_ps; in amdgpu_dpm_pick_power_state()
930 if (adev->pm.dpm.uvd_ps) { in amdgpu_dpm_pick_power_state()
931 return adev->pm.dpm.uvd_ps; in amdgpu_dpm_pick_power_state()
966 if (adev->pm.dpm.user_state != adev->pm.dpm.state) { in amdgpu_dpm_change_power_state_locked()
968 if ((!adev->pm.dpm.thermal_active) && in amdgpu_dpm_change_power_state_locked()
969 (!adev->pm.dpm.uvd_active)) in amdgpu_dpm_change_power_state_locked()
970 adev->pm.dpm.state = adev->pm.dpm.user_state; in amdgpu_dpm_change_power_state_locked()
972 dpm_state = adev->pm.dpm.state; in amdgpu_dpm_change_power_state_locked()
976 adev->pm.dpm.requested_ps = ps; in amdgpu_dpm_change_power_state_locked()
982 amdgpu_dpm_print_power_state(adev, adev->pm.dpm.current_ps); in amdgpu_dpm_change_power_state_locked()
984 amdgpu_dpm_print_power_state(adev, adev->pm.dpm.requested_ps); in amdgpu_dpm_change_power_state_locked()
988 ps->vce_active = adev->pm.dpm.vce_active; in amdgpu_dpm_change_power_state_locked()
997 …if (0 != amdgpu_dpm_check_state_equal(adev, adev->pm.dpm.current_ps, adev->pm.dpm.requested_ps, &e… in amdgpu_dpm_change_power_state_locked()
1009 adev->pm.dpm.current_active_crtcs = adev->pm.dpm.new_active_crtcs; in amdgpu_dpm_change_power_state_locked()
1010 adev->pm.dpm.current_active_crtc_count = adev->pm.dpm.new_active_crtc_count; in amdgpu_dpm_change_power_state_locked()
1013 if (adev->pm.dpm.thermal_active) { in amdgpu_dpm_change_power_state_locked()
1014 enum amd_dpm_forced_level level = adev->pm.dpm.forced_level; in amdgpu_dpm_change_power_state_locked()
1018 adev->pm.dpm.forced_level = level; in amdgpu_dpm_change_power_state_locked()
1021 pp_funcs->force_performance_level(adev, adev->pm.dpm.forced_level); in amdgpu_dpm_change_power_state_locked()
1041 pm.dpm.thermal.work); in amdgpu_dpm_thermal_work_handler()
1054 if (temp < adev->pm.dpm.thermal.min_temp) in amdgpu_dpm_thermal_work_handler()
1056 dpm_state = adev->pm.dpm.user_state; in amdgpu_dpm_thermal_work_handler()
1058 if (adev->pm.dpm.thermal.high_to_low) in amdgpu_dpm_thermal_work_handler()
1060 dpm_state = adev->pm.dpm.user_state; in amdgpu_dpm_thermal_work_handler()
1064 adev->pm.dpm.thermal_active = true; in amdgpu_dpm_thermal_work_handler()
1066 adev->pm.dpm.thermal_active = false; in amdgpu_dpm_thermal_work_handler()
1068 adev->pm.dpm.state = dpm_state; in amdgpu_dpm_thermal_work_handler()