Lines Matching refs:dpm
1854 struct si_power_info *pi = adev->pm.dpm.priv; in si_get_pi()
1927 u32 p_limit1 = adev->pm.dpm.tdp_limit; in si_update_dte_from_pl2()
1928 u32 p_limit2 = adev->pm.dpm.near_tdp_limit; in si_update_dte_from_pl2()
1956 struct rv7xx_power_info *pi = adev->pm.dpm.priv; in rv770_get_pi()
1963 struct ni_power_info *pi = adev->pm.dpm.priv; in ni_get_pi()
2217 if (tdp_adjustment > (u32)adev->pm.dpm.tdp_od_limit) in si_calculate_adjusted_tdp_limits()
2220 max_tdp_limit = ((100 + 100) * adev->pm.dpm.tdp_limit) / 100; in si_calculate_adjusted_tdp_limits()
2223 *tdp_limit = ((100 + tdp_adjustment) * adev->pm.dpm.tdp_limit) / 100; in si_calculate_adjusted_tdp_limits()
2224 *near_tdp_limit = adev->pm.dpm.near_tdp_limit_adjusted + (*tdp_limit - adev->pm.dpm.tdp_limit); in si_calculate_adjusted_tdp_limits()
2226 *tdp_limit = ((100 - tdp_adjustment) * adev->pm.dpm.tdp_limit) / 100; in si_calculate_adjusted_tdp_limits()
2227 adjustment_delta = adev->pm.dpm.tdp_limit - *tdp_limit; in si_calculate_adjusted_tdp_limits()
2228 if (adjustment_delta < adev->pm.dpm.near_tdp_limit_adjusted) in si_calculate_adjusted_tdp_limits()
2229 *near_tdp_limit = adev->pm.dpm.near_tdp_limit_adjusted - adjustment_delta; in si_calculate_adjusted_tdp_limits()
2251 struct amdgpu_ppm_table *ppm = adev->pm.dpm.dyn_state.ppm_table; in si_populate_smc_tdp_limits()
2264 adev->pm.dpm.tdp_adjustment, in si_populate_smc_tdp_limits()
2321 cpu_to_be32(si_scale_power_for_smc(adev->pm.dpm.near_tdp_limit_adjusted, scaling_factor) * 1000); in si_populate_smc_tdp_limits_2()
2323 …cpu_to_be32(si_scale_power_for_smc((adev->pm.dpm.near_tdp_limit_adjusted * SISLANDS_DPM2_TDP_SAFE_… in si_populate_smc_tdp_limits_2()
2375 struct evergreen_power_info *pi = adev->pm.dpm.priv; in evergreen_get_pi()
2489 if (adev->pm.dpm.sq_ramping_threshold == 0) in si_populate_sq_ramping_values()
2511 if ((state->performance_levels[i].sclk >= adev->pm.dpm.sq_ramping_threshold) && in si_populate_sq_ramping_values()
2632 &adev->pm.dpm.dyn_state.cac_leakage_table; in si_get_cac_std_voltage_max_min()
2768 si_pi->dyn_powertune_data.cac_leakage = adev->pm.dpm.cac_leakage; in si_initialize_smc_cac_tables()
2795 load_line_slope = ((u32)adev->pm.dpm.load_line_slope << SMC_SISLANDS_SCALE_R) / 100; in si_initialize_smc_cac_tables()
3036 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; in si_get_vce_clock_voltage()
3151 adev->pm.dpm.current_ps = &eg_pi->current_rps; in ni_update_current_ps()
3164 adev->pm.dpm.requested_ps = &eg_pi->requested_rps; in ni_update_requested_ps()
3234 return btc_find_valid_clock(&adev->pm.dpm.dyn_state.valid_mclk_values, in btc_get_valid_mclk()
3241 return btc_find_valid_clock(&adev->pm.dpm.dyn_state.valid_sclk_values, in btc_get_valid_sclk()
3294 if (((pl->mclk + (pl->sclk - 1)) / pl->sclk) > adev->pm.dpm.dyn_state.mclk_sclk_ratio) in btc_adjust_clock_combinations()
3298 (adev->pm.dpm.dyn_state.mclk_sclk_ratio - 1)) / in btc_adjust_clock_combinations()
3299 adev->pm.dpm.dyn_state.mclk_sclk_ratio); in btc_adjust_clock_combinations()
3301 if ((pl->sclk - pl->mclk) > adev->pm.dpm.dyn_state.sclk_mclk_delta) in btc_adjust_clock_combinations()
3305 adev->pm.dpm.dyn_state.sclk_mclk_delta); in btc_adjust_clock_combinations()
3320 if ((*vddc - *vddci) > adev->pm.dpm.dyn_state.vddc_vddci_delta) { in btc_apply_voltage_delta_rules()
3322 (*vddc - adev->pm.dpm.dyn_state.vddc_vddci_delta)); in btc_apply_voltage_delta_rules()
3326 if ((*vddci - *vddc) > adev->pm.dpm.dyn_state.vddc_vddci_delta) { in btc_apply_voltage_delta_rules()
3328 (*vddci - adev->pm.dpm.dyn_state.vddc_vddci_delta)); in btc_apply_voltage_delta_rules()
3461 rps->evclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].evclk; in si_apply_state_adjust_rules()
3462 rps->ecclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].ecclk; in si_apply_state_adjust_rules()
3470 if ((adev->pm.dpm.new_active_crtc_count > 1) || in si_apply_state_adjust_rules()
3480 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac; in si_apply_state_adjust_rules()
3482 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc; in si_apply_state_adjust_rules()
3502 btc_get_max_clock_from_voltage_dependency_table(&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk, in si_apply_state_adjust_rules()
3504 btc_get_max_clock_from_voltage_dependency_table(&adev->pm.dpm.dyn_state.vddci_dependency_on_mclk, in si_apply_state_adjust_rules()
3506 btc_get_max_clock_from_voltage_dependency_table(&adev->pm.dpm.dyn_state.vddc_dependency_on_mclk, in si_apply_state_adjust_rules()
3551 if (sclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk) in si_apply_state_adjust_rules()
3552 sclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk; in si_apply_state_adjust_rules()
3553 if (mclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].mclk) in si_apply_state_adjust_rules()
3554 mclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].mclk; in si_apply_state_adjust_rules()
3608 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk, in si_apply_state_adjust_rules()
3611 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddci_dependency_on_mclk, in si_apply_state_adjust_rules()
3614 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddc_dependency_on_mclk, in si_apply_state_adjust_rules()
3617 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk, in si_apply_state_adjust_rules()
3631 if (ps->performance_levels[i].vddc > adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc) in si_apply_state_adjust_rules()
3858 struct amdgpu_ps *rps = adev->pm.dpm.current_ps; in si_dpm_force_performance_level()
3882 adev->pm.dpm.forced_level = level; in si_dpm_force_performance_level()
4103 voltage_response_time = (u32)adev->pm.dpm.voltage_response_time; in si_program_response_times()
4147 if (adev->pm.dpm.new_active_crtc_count > 0) in si_program_display_gap()
4152 if (adev->pm.dpm.new_active_crtc_count > 1) in si_program_display_gap()
4162 if ((adev->pm.dpm.new_active_crtc_count > 0) && in si_program_display_gap()
4163 (!(adev->pm.dpm.new_active_crtcs & (1 << pipe)))) { in si_program_display_gap()
4166 if (adev->pm.dpm.new_active_crtcs & (1 << i)) in si_program_display_gap()
4183 si_notify_smc_display_change(adev, adev->pm.dpm.new_active_crtc_count > 0); in si_program_display_gap()
4433 &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk, in si_construct_voltage_tables()
4454 &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk, in si_construct_voltage_tables()
4550 &adev->pm.dpm.dyn_state.phase_shedding_limits_table)) { in si_populate_smc_voltage_tables()
4612 if (adev->pm.dpm.dyn_state.cac_leakage_table.entries) { in si_get_std_voltage_value()
4613 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE) { in si_get_std_voltage_value()
4614 if (adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL) in si_get_std_voltage_value()
4617 …for (v_index = 0; (u32)v_index < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { in si_get_std_voltage_value()
4619 (u16)adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { in si_get_std_voltage_value()
4621 if ((u32)v_index < adev->pm.dpm.dyn_state.cac_leakage_table.count) in si_get_std_voltage_value()
4623 adev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc; in si_get_std_voltage_value()
4626 …adev->pm.dpm.dyn_state.cac_leakage_table.entries[adev->pm.dpm.dyn_state.cac_leakage_table.count-1]… in si_get_std_voltage_value()
4632 …for (v_index = 0; (u32)v_index < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { in si_get_std_voltage_value()
4634 (u16)adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { in si_get_std_voltage_value()
4636 if ((u32)v_index < adev->pm.dpm.dyn_state.cac_leakage_table.count) in si_get_std_voltage_value()
4638 adev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc; in si_get_std_voltage_value()
4641 …adev->pm.dpm.dyn_state.cac_leakage_table.entries[adev->pm.dpm.dyn_state.cac_leakage_table.count-1]… in si_get_std_voltage_value()
4647 if ((u32)voltage->index < adev->pm.dpm.dyn_state.cac_leakage_table.count) in si_get_std_voltage_value()
4648 *std_voltage = adev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc; in si_get_std_voltage_value()
4902 &adev->pm.dpm.dyn_state.phase_shedding_limits_table, in si_populate_smc_initial_state()
5011 &adev->pm.dpm.dyn_state.phase_shedding_limits_table, in si_populate_smc_acpi_state()
5039 &adev->pm.dpm.dyn_state.phase_shedding_limits_table, in si_populate_smc_acpi_state()
5179 struct amdgpu_ps *amdgpu_boot_state = adev->pm.dpm.boot_ps; in si_init_smc_table()
5201 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC) in si_init_smc_table()
5204 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) { in si_init_smc_table()
5209 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC) in si_init_smc_table()
5215 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY) in si_init_smc_table()
5218 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE) { in si_init_smc_table()
5220 vr_hot_gpio = adev->pm.dpm.backbias_response_time; in si_init_smc_table()
5488 (adev->pm.dpm.new_active_crtc_count <= 2)) { in si_convert_power_level_to_smc()
5553 &adev->pm.dpm.dyn_state.phase_shedding_limits_table, in si_convert_power_level_to_smc()
5643 for (i = 0; i < adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count; i++) { in si_is_state_ulv_compatible()
5645 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].clk) { in si_is_state_ulv_compatible()
5647 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].v) in si_is_state_ulv_compatible()
5801 if (adev->pm.dpm.new_active_crtc_count == 0) in si_upload_smc_data()
5805 if (adev->pm.dpm.new_active_crtcs & (1 << i)) { in si_upload_smc_data()
6377 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk); in si_patch_dependency_tables_based_on_leakage()
6381 &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk); in si_patch_dependency_tables_based_on_leakage()
6385 &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk); in si_patch_dependency_tables_based_on_leakage()
6456 adev->pm.dpm.thermal.min_temp = low_temp; in si_thermal_set_temperature_range()
6457 adev->pm.dpm.thermal.max_temp = high_temp; in si_thermal_set_temperature_range()
6496 adev->pm.dpm.fan.ucode_fan_control = false; in si_thermal_setup_fan_table()
6503 adev->pm.dpm.fan.ucode_fan_control = false; in si_thermal_setup_fan_table()
6507 tmp64 = (u64)adev->pm.dpm.fan.pwm_min * duty100; in si_thermal_setup_fan_table()
6511 t_diff1 = adev->pm.dpm.fan.t_med - adev->pm.dpm.fan.t_min; in si_thermal_setup_fan_table()
6512 t_diff2 = adev->pm.dpm.fan.t_high - adev->pm.dpm.fan.t_med; in si_thermal_setup_fan_table()
6514 pwm_diff1 = adev->pm.dpm.fan.pwm_med - adev->pm.dpm.fan.pwm_min; in si_thermal_setup_fan_table()
6515 pwm_diff2 = adev->pm.dpm.fan.pwm_high - adev->pm.dpm.fan.pwm_med; in si_thermal_setup_fan_table()
6520 fan_table.temp_min = cpu_to_be16((50 + adev->pm.dpm.fan.t_min) / 100); in si_thermal_setup_fan_table()
6521 fan_table.temp_med = cpu_to_be16((50 + adev->pm.dpm.fan.t_med) / 100); in si_thermal_setup_fan_table()
6522 fan_table.temp_max = cpu_to_be16((50 + adev->pm.dpm.fan.t_max) / 100); in si_thermal_setup_fan_table()
6526 fan_table.hys_down = cpu_to_be16(adev->pm.dpm.fan.t_hyst); in si_thermal_setup_fan_table()
6532 fan_table.refresh_period = cpu_to_be32((adev->pm.dpm.fan.cycle_delay * in si_thermal_setup_fan_table()
6547 adev->pm.dpm.fan.ucode_fan_control = false; in si_thermal_setup_fan_table()
6651 if (adev->pm.dpm.fan.ucode_fan_control) in si_dpm_set_fan_control_mode()
6656 if (adev->pm.dpm.fan.ucode_fan_control) in si_dpm_set_fan_control_mode()
6721 if (adev->pm.dpm.fan.ucode_fan_control)
6754 if (adev->pm.dpm.fan.ucode_fan_control) { in si_thermal_start_smc_fan_control()
6786 if (adev->pm.dpm.fan.ucode_fan_control) { in si_thermal_start_thermal_controller()
6815 struct amdgpu_ps *boot_ps = adev->pm.dpm.boot_ps; in si_dpm_enable()
6948 struct amdgpu_ps *boot_ps = adev->pm.dpm.boot_ps; in si_dpm_disable()
6973 struct amdgpu_ps requested_ps = *adev->pm.dpm.requested_ps; in si_dpm_pre_set_power_state()
6984 struct amdgpu_ps *new_ps = adev->pm.dpm.requested_ps; in si_power_control_set_level()
7174 adev->pm.dpm.boot_ps = rps; in si_parse_pplib_non_clock_info()
7176 adev->pm.dpm.uvd_ps = rps; in si_parse_pplib_non_clock_info()
7248 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk; in si_parse_pplib_clock_info()
7249 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk; in si_parse_pplib_clock_info()
7250 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc; in si_parse_pplib_clock_info()
7251 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci; in si_parse_pplib_clock_info()
7294 adev->pm.dpm.ps = kcalloc(state_array->ucNumEntries, in si_parse_power_table()
7297 if (!adev->pm.dpm.ps) in si_parse_power_table()
7300 for (adev->pm.dpm.num_ps = 0, i = 0; i < state_array->ucNumEntries; i++) { in si_parse_power_table()
7309 adev->pm.dpm.ps[i].ps_priv = ps; in si_parse_power_table()
7310 si_parse_pplib_non_clock_info(adev, &adev->pm.dpm.ps[i], in si_parse_power_table()
7325 &adev->pm.dpm.ps[i], k, in si_parse_power_table()
7330 adev->pm.dpm.num_ps++; in si_parse_power_table()
7334 for (i = 0; i < adev->pm.dpm.num_of_vce_states; i++) { in si_parse_power_table()
7336 clock_array_index = adev->pm.dpm.vce_states[i].clk_idx; in si_parse_power_table()
7343 adev->pm.dpm.vce_states[i].sclk = sclk; in si_parse_power_table()
7344 adev->pm.dpm.vce_states[i].mclk = mclk; in si_parse_power_table()
7362 adev->pm.dpm.priv = si_pi; in si_dpm_init()
7395 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries = in si_dpm_init()
7399 if (!adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) { in si_dpm_init()
7403 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4; in si_dpm_init()
7404 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0; in si_dpm_init()
7405 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0; in si_dpm_init()
7406 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000; in si_dpm_init()
7407 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720; in si_dpm_init()
7408 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000; in si_dpm_init()
7409 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810; in si_dpm_init()
7410 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000; in si_dpm_init()
7411 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900; in si_dpm_init()
7413 if (adev->pm.dpm.voltage_response_time == 0) in si_dpm_init()
7414 adev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT; in si_dpm_init()
7415 if (adev->pm.dpm.backbias_response_time == 0) in si_dpm_init()
7416 adev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT; in si_dpm_init()
7493 adev->pm.dpm.dyn_state.mclk_sclk_ratio = 4; in si_dpm_init()
7494 adev->pm.dpm.dyn_state.sclk_mclk_delta = 15000; in si_dpm_init()
7495 adev->pm.dpm.dyn_state.vddc_vddci_delta = 200; in si_dpm_init()
7496 adev->pm.dpm.dyn_state.valid_sclk_values.count = 0; in si_dpm_init()
7497 adev->pm.dpm.dyn_state.valid_sclk_values.values = NULL; in si_dpm_init()
7498 adev->pm.dpm.dyn_state.valid_mclk_values.count = 0; in si_dpm_init()
7499 adev->pm.dpm.dyn_state.valid_mclk_values.values = NULL; in si_dpm_init()
7504 if ((adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) || in si_dpm_init()
7505 (adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0)) in si_dpm_init()
7506 adev->pm.dpm.dyn_state.max_clock_voltage_on_dc = in si_dpm_init()
7507 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac; in si_dpm_init()
7518 if (adev->pm.dpm.ps) in si_dpm_fini()
7519 for (i = 0; i < adev->pm.dpm.num_ps; i++) in si_dpm_fini()
7520 kfree(adev->pm.dpm.ps[i].ps_priv); in si_dpm_fini()
7521 kfree(adev->pm.dpm.ps); in si_dpm_fini()
7522 kfree(adev->pm.dpm.priv); in si_dpm_fini()
7523 kfree(adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries); in si_dpm_fini()
7609 adev->pm.dpm.thermal.high_to_low = false; in si_dpm_process_interrupt()
7614 adev->pm.dpm.thermal.high_to_low = true; in si_dpm_process_interrupt()
7622 schedule_work(&adev->pm.dpm.thermal.work); in si_dpm_process_interrupt()
7731 ret = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 230, &adev->pm.dpm.thermal.irq); in si_dpm_sw_init()
7735 ret = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 231, &adev->pm.dpm.thermal.irq); in si_dpm_sw_init()
7740 adev->pm.dpm.state = POWER_STATE_TYPE_BALANCED; in si_dpm_sw_init()
7741 adev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED; in si_dpm_sw_init()
7742 adev->pm.dpm.forced_level = AMD_DPM_FORCED_LEVEL_AUTO; in si_dpm_sw_init()
7756 INIT_WORK(&adev->pm.dpm.thermal.work, amdgpu_dpm_thermal_work_handler); in si_dpm_sw_init()
7760 adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps; in si_dpm_sw_init()
7777 flush_work(&adev->pm.dpm.thermal.work); in si_dpm_sw_fini()
7821 adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps; in si_dpm_suspend()
8103 adev->pm.dpm.thermal.irq.num_types = AMDGPU_THERMAL_IRQ_LAST; in si_dpm_set_irq_funcs()
8104 adev->pm.dpm.thermal.irq.funcs = &si_dpm_irq_funcs; in si_dpm_set_irq_funcs()