Lines Matching refs:hwmgr
41 struct pp_hwmgr *hwmgr; in amd_powerplay_create() local
46 hwmgr = kzalloc(sizeof(struct pp_hwmgr), GFP_KERNEL); in amd_powerplay_create()
47 if (hwmgr == NULL) in amd_powerplay_create()
50 hwmgr->adev = adev; in amd_powerplay_create()
51 hwmgr->not_vf = !amdgpu_sriov_vf(adev); in amd_powerplay_create()
52 hwmgr->device = amdgpu_cgs_create_device(adev); in amd_powerplay_create()
53 mutex_init(&hwmgr->msg_lock); in amd_powerplay_create()
54 hwmgr->chip_family = adev->family; in amd_powerplay_create()
55 hwmgr->chip_id = adev->asic_type; in amd_powerplay_create()
56 hwmgr->feature_mask = adev->pm.pp_feature; in amd_powerplay_create()
57 hwmgr->display_config = &adev->pm.pm_display_cfg; in amd_powerplay_create()
58 adev->powerplay.pp_handle = hwmgr; in amd_powerplay_create()
66 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle; in amd_powerplay_destroy() local
68 mutex_destroy(&hwmgr->msg_lock); in amd_powerplay_destroy()
70 kfree(hwmgr->hardcode_pp_table); in amd_powerplay_destroy()
71 hwmgr->hardcode_pp_table = NULL; in amd_powerplay_destroy()
73 kfree(hwmgr); in amd_powerplay_destroy()
74 hwmgr = NULL; in amd_powerplay_destroy()
97 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle; in pp_sw_init() local
100 ret = hwmgr_sw_init(hwmgr); in pp_sw_init()
110 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle; in pp_sw_fini() local
112 hwmgr_sw_fini(hwmgr); in pp_sw_fini()
123 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle; in pp_hw_init() local
125 ret = hwmgr_hw_init(hwmgr); in pp_hw_init()
136 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle; in pp_hw_fini() local
138 hwmgr_hw_fini(hwmgr); in pp_hw_fini()
148 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle; in pp_reserve_vram_for_smu() local
159 if (hwmgr->hwmgr_func->notify_cac_buffer_info) in pp_reserve_vram_for_smu()
160 r = hwmgr->hwmgr_func->notify_cac_buffer_info(hwmgr, in pp_reserve_vram_for_smu()
177 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle; in pp_late_init() local
179 if (hwmgr && hwmgr->pm_en) in pp_late_init()
180 hwmgr_handle_task(hwmgr, in pp_late_init()
222 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle; in pp_suspend() local
224 return hwmgr_suspend(hwmgr); in pp_suspend()
230 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle; in pp_resume() local
232 return hwmgr_resume(hwmgr); in pp_resume()
275 struct pp_hwmgr *hwmgr = handle; in pp_dpm_load_fw() local
277 if (!hwmgr || !hwmgr->smumgr_funcs || !hwmgr->smumgr_funcs->start_smu) in pp_dpm_load_fw()
280 if (hwmgr->smumgr_funcs->start_smu(hwmgr)) { in pp_dpm_load_fw()
295 struct pp_hwmgr *hwmgr = handle; in pp_set_clockgating_by_smu() local
297 if (!hwmgr || !hwmgr->pm_en) in pp_set_clockgating_by_smu()
300 if (hwmgr->hwmgr_func->update_clock_gatings == NULL) { in pp_set_clockgating_by_smu()
305 return hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id); in pp_set_clockgating_by_smu()
308 static void pp_dpm_en_umd_pstate(struct pp_hwmgr *hwmgr, in pp_dpm_en_umd_pstate() argument
316 if (!(hwmgr->dpm_level & profile_mode_mask)) { in pp_dpm_en_umd_pstate()
319 hwmgr->saved_dpm_level = hwmgr->dpm_level; in pp_dpm_en_umd_pstate()
320 hwmgr->en_umd_pstate = true; in pp_dpm_en_umd_pstate()
326 *level = hwmgr->saved_dpm_level; in pp_dpm_en_umd_pstate()
327 hwmgr->en_umd_pstate = false; in pp_dpm_en_umd_pstate()
335 struct pp_hwmgr *hwmgr = handle; in pp_dpm_force_performance_level() local
337 if (!hwmgr || !hwmgr->pm_en) in pp_dpm_force_performance_level()
340 if (level == hwmgr->dpm_level) in pp_dpm_force_performance_level()
343 pp_dpm_en_umd_pstate(hwmgr, &level); in pp_dpm_force_performance_level()
344 hwmgr->request_dpm_level = level; in pp_dpm_force_performance_level()
345 hwmgr_handle_task(hwmgr, AMD_PP_TASK_READJUST_POWER_STATE, NULL); in pp_dpm_force_performance_level()
353 struct pp_hwmgr *hwmgr = handle; in pp_dpm_get_performance_level() local
355 if (!hwmgr || !hwmgr->pm_en) in pp_dpm_get_performance_level()
358 return hwmgr->dpm_level; in pp_dpm_get_performance_level()
363 struct pp_hwmgr *hwmgr = handle; in pp_dpm_get_sclk() local
365 if (!hwmgr || !hwmgr->pm_en) in pp_dpm_get_sclk()
368 if (hwmgr->hwmgr_func->get_sclk == NULL) { in pp_dpm_get_sclk()
372 return hwmgr->hwmgr_func->get_sclk(hwmgr, low); in pp_dpm_get_sclk()
377 struct pp_hwmgr *hwmgr = handle; in pp_dpm_get_mclk() local
379 if (!hwmgr || !hwmgr->pm_en) in pp_dpm_get_mclk()
382 if (hwmgr->hwmgr_func->get_mclk == NULL) { in pp_dpm_get_mclk()
386 return hwmgr->hwmgr_func->get_mclk(hwmgr, low); in pp_dpm_get_mclk()
391 struct pp_hwmgr *hwmgr = handle; in pp_dpm_powergate_vce() local
393 if (!hwmgr || !hwmgr->pm_en) in pp_dpm_powergate_vce()
396 if (hwmgr->hwmgr_func->powergate_vce == NULL) { in pp_dpm_powergate_vce()
400 hwmgr->hwmgr_func->powergate_vce(hwmgr, gate); in pp_dpm_powergate_vce()
405 struct pp_hwmgr *hwmgr = handle; in pp_dpm_powergate_uvd() local
407 if (!hwmgr || !hwmgr->pm_en) in pp_dpm_powergate_uvd()
410 if (hwmgr->hwmgr_func->powergate_uvd == NULL) { in pp_dpm_powergate_uvd()
414 hwmgr->hwmgr_func->powergate_uvd(hwmgr, gate); in pp_dpm_powergate_uvd()
420 struct pp_hwmgr *hwmgr = handle; in pp_dpm_dispatch_tasks() local
422 if (!hwmgr || !hwmgr->pm_en) in pp_dpm_dispatch_tasks()
425 return hwmgr_handle_task(hwmgr, task_id, user_state); in pp_dpm_dispatch_tasks()
430 struct pp_hwmgr *hwmgr = handle; in pp_dpm_get_current_power_state() local
434 if (!hwmgr || !hwmgr->pm_en || !hwmgr->current_ps) in pp_dpm_get_current_power_state()
437 state = hwmgr->current_ps; in pp_dpm_get_current_power_state()
462 struct pp_hwmgr *hwmgr = handle; in pp_dpm_set_fan_control_mode() local
464 if (!hwmgr || !hwmgr->pm_en) in pp_dpm_set_fan_control_mode()
467 if (hwmgr->hwmgr_func->set_fan_control_mode == NULL) in pp_dpm_set_fan_control_mode()
473 hwmgr->hwmgr_func->set_fan_control_mode(hwmgr, mode); in pp_dpm_set_fan_control_mode()
480 struct pp_hwmgr *hwmgr = handle; in pp_dpm_get_fan_control_mode() local
482 if (!hwmgr || !hwmgr->pm_en) in pp_dpm_get_fan_control_mode()
485 if (hwmgr->hwmgr_func->get_fan_control_mode == NULL) in pp_dpm_get_fan_control_mode()
491 *fan_mode = hwmgr->hwmgr_func->get_fan_control_mode(hwmgr); in pp_dpm_get_fan_control_mode()
497 struct pp_hwmgr *hwmgr = handle; in pp_dpm_set_fan_speed_pwm() local
499 if (!hwmgr || !hwmgr->pm_en) in pp_dpm_set_fan_speed_pwm()
502 if (hwmgr->hwmgr_func->set_fan_speed_pwm == NULL) in pp_dpm_set_fan_speed_pwm()
508 return hwmgr->hwmgr_func->set_fan_speed_pwm(hwmgr, speed); in pp_dpm_set_fan_speed_pwm()
513 struct pp_hwmgr *hwmgr = handle; in pp_dpm_get_fan_speed_pwm() local
515 if (!hwmgr || !hwmgr->pm_en) in pp_dpm_get_fan_speed_pwm()
518 if (hwmgr->hwmgr_func->get_fan_speed_pwm == NULL) in pp_dpm_get_fan_speed_pwm()
524 return hwmgr->hwmgr_func->get_fan_speed_pwm(hwmgr, speed); in pp_dpm_get_fan_speed_pwm()
529 struct pp_hwmgr *hwmgr = handle; in pp_dpm_get_fan_speed_rpm() local
531 if (!hwmgr || !hwmgr->pm_en) in pp_dpm_get_fan_speed_rpm()
534 if (hwmgr->hwmgr_func->get_fan_speed_rpm == NULL) in pp_dpm_get_fan_speed_rpm()
540 return hwmgr->hwmgr_func->get_fan_speed_rpm(hwmgr, rpm); in pp_dpm_get_fan_speed_rpm()
545 struct pp_hwmgr *hwmgr = handle; in pp_dpm_set_fan_speed_rpm() local
547 if (!hwmgr || !hwmgr->pm_en) in pp_dpm_set_fan_speed_rpm()
550 if (hwmgr->hwmgr_func->set_fan_speed_rpm == NULL) in pp_dpm_set_fan_speed_rpm()
556 return hwmgr->hwmgr_func->set_fan_speed_rpm(hwmgr, rpm); in pp_dpm_set_fan_speed_rpm()
562 struct pp_hwmgr *hwmgr = handle; in pp_dpm_get_pp_num_states() local
567 if (!hwmgr || !hwmgr->pm_en ||!hwmgr->ps) in pp_dpm_get_pp_num_states()
570 data->nums = hwmgr->num_ps; in pp_dpm_get_pp_num_states()
572 for (i = 0; i < hwmgr->num_ps; i++) { in pp_dpm_get_pp_num_states()
574 ((unsigned long)hwmgr->ps + i * hwmgr->ps_size); in pp_dpm_get_pp_num_states()
597 struct pp_hwmgr *hwmgr = handle; in pp_dpm_get_pp_table() local
599 if (!hwmgr || !hwmgr->pm_en ||!hwmgr->soft_pp_table) in pp_dpm_get_pp_table()
602 *table = (char *)hwmgr->soft_pp_table; in pp_dpm_get_pp_table()
603 return hwmgr->soft_pp_table_size; in pp_dpm_get_pp_table()
608 struct pp_hwmgr *hwmgr = handle; in amd_powerplay_reset() local
611 ret = hwmgr_hw_fini(hwmgr); in amd_powerplay_reset()
615 ret = hwmgr_hw_init(hwmgr); in amd_powerplay_reset()
619 return hwmgr_handle_task(hwmgr, AMD_PP_TASK_COMPLETE_INIT, NULL); in amd_powerplay_reset()
624 struct pp_hwmgr *hwmgr = handle; in pp_dpm_set_pp_table() local
627 if (!hwmgr || !hwmgr->pm_en) in pp_dpm_set_pp_table()
630 if (!hwmgr->hardcode_pp_table) { in pp_dpm_set_pp_table()
631 hwmgr->hardcode_pp_table = kmemdup(hwmgr->soft_pp_table, in pp_dpm_set_pp_table()
632 hwmgr->soft_pp_table_size, in pp_dpm_set_pp_table()
634 if (!hwmgr->hardcode_pp_table) in pp_dpm_set_pp_table()
638 memcpy(hwmgr->hardcode_pp_table, buf, size); in pp_dpm_set_pp_table()
640 hwmgr->soft_pp_table = hwmgr->hardcode_pp_table; in pp_dpm_set_pp_table()
646 if (hwmgr->hwmgr_func->avfs_control) in pp_dpm_set_pp_table()
647 ret = hwmgr->hwmgr_func->avfs_control(hwmgr, false); in pp_dpm_set_pp_table()
655 struct pp_hwmgr *hwmgr = handle; in pp_dpm_force_clock_level() local
657 if (!hwmgr || !hwmgr->pm_en) in pp_dpm_force_clock_level()
660 if (hwmgr->hwmgr_func->force_clock_level == NULL) { in pp_dpm_force_clock_level()
665 if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { in pp_dpm_force_clock_level()
670 return hwmgr->hwmgr_func->force_clock_level(hwmgr, type, mask); in pp_dpm_force_clock_level()
678 struct pp_hwmgr *hwmgr = handle; in pp_dpm_emit_clock_levels() local
680 if (!hwmgr || !hwmgr->pm_en) in pp_dpm_emit_clock_levels()
683 if (!hwmgr->hwmgr_func->emit_clock_levels) in pp_dpm_emit_clock_levels()
686 return hwmgr->hwmgr_func->emit_clock_levels(hwmgr, type, buf, offset); in pp_dpm_emit_clock_levels()
692 struct pp_hwmgr *hwmgr = handle; in pp_dpm_print_clock_levels() local
694 if (!hwmgr || !hwmgr->pm_en) in pp_dpm_print_clock_levels()
697 if (hwmgr->hwmgr_func->print_clock_levels == NULL) { in pp_dpm_print_clock_levels()
701 return hwmgr->hwmgr_func->print_clock_levels(hwmgr, type, buf); in pp_dpm_print_clock_levels()
706 struct pp_hwmgr *hwmgr = handle; in pp_dpm_get_sclk_od() local
708 if (!hwmgr || !hwmgr->pm_en) in pp_dpm_get_sclk_od()
711 if (hwmgr->hwmgr_func->get_sclk_od == NULL) { in pp_dpm_get_sclk_od()
715 return hwmgr->hwmgr_func->get_sclk_od(hwmgr); in pp_dpm_get_sclk_od()
720 struct pp_hwmgr *hwmgr = handle; in pp_dpm_set_sclk_od() local
722 if (!hwmgr || !hwmgr->pm_en) in pp_dpm_set_sclk_od()
725 if (hwmgr->hwmgr_func->set_sclk_od == NULL) { in pp_dpm_set_sclk_od()
730 return hwmgr->hwmgr_func->set_sclk_od(hwmgr, value); in pp_dpm_set_sclk_od()
735 struct pp_hwmgr *hwmgr = handle; in pp_dpm_get_mclk_od() local
737 if (!hwmgr || !hwmgr->pm_en) in pp_dpm_get_mclk_od()
740 if (hwmgr->hwmgr_func->get_mclk_od == NULL) { in pp_dpm_get_mclk_od()
744 return hwmgr->hwmgr_func->get_mclk_od(hwmgr); in pp_dpm_get_mclk_od()
749 struct pp_hwmgr *hwmgr = handle; in pp_dpm_set_mclk_od() local
751 if (!hwmgr || !hwmgr->pm_en) in pp_dpm_set_mclk_od()
754 if (hwmgr->hwmgr_func->set_mclk_od == NULL) { in pp_dpm_set_mclk_od()
758 return hwmgr->hwmgr_func->set_mclk_od(hwmgr, value); in pp_dpm_set_mclk_od()
764 struct pp_hwmgr *hwmgr = handle; in pp_dpm_read_sensor() local
766 if (!hwmgr || !hwmgr->pm_en || !value) in pp_dpm_read_sensor()
771 *((uint32_t *)value) = hwmgr->pstate_sclk * 100; in pp_dpm_read_sensor()
774 *((uint32_t *)value) = hwmgr->pstate_mclk * 100; in pp_dpm_read_sensor()
777 *((uint32_t *)value) = hwmgr->pstate_sclk_peak * 100; in pp_dpm_read_sensor()
780 *((uint32_t *)value) = hwmgr->pstate_mclk_peak * 100; in pp_dpm_read_sensor()
783 *((uint32_t *)value) = hwmgr->thermal_controller.fanInfo.ulMinRPM; in pp_dpm_read_sensor()
786 *((uint32_t *)value) = hwmgr->thermal_controller.fanInfo.ulMaxRPM; in pp_dpm_read_sensor()
789 return hwmgr->hwmgr_func->read_sensor(hwmgr, idx, value, size); in pp_dpm_read_sensor()
796 struct pp_hwmgr *hwmgr = handle; in pp_dpm_get_vce_clock_state() local
798 if (!hwmgr || !hwmgr->pm_en) in pp_dpm_get_vce_clock_state()
801 if (idx < hwmgr->num_vce_state_tables) in pp_dpm_get_vce_clock_state()
802 return &hwmgr->vce_states[idx]; in pp_dpm_get_vce_clock_state()
808 struct pp_hwmgr *hwmgr = handle; in pp_get_power_profile_mode() local
810 if (!hwmgr || !hwmgr->pm_en || !hwmgr->hwmgr_func->get_power_profile_mode) in pp_get_power_profile_mode()
815 return hwmgr->hwmgr_func->get_power_profile_mode(hwmgr, buf); in pp_get_power_profile_mode()
820 struct pp_hwmgr *hwmgr = handle; in pp_set_power_profile_mode() local
822 if (!hwmgr || !hwmgr->pm_en || !hwmgr->hwmgr_func->set_power_profile_mode) in pp_set_power_profile_mode()
825 if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { in pp_set_power_profile_mode()
830 return hwmgr->hwmgr_func->set_power_profile_mode(hwmgr, input, size); in pp_set_power_profile_mode()
835 struct pp_hwmgr *hwmgr = handle; in pp_set_fine_grain_clk_vol() local
837 if (!hwmgr || !hwmgr->pm_en) in pp_set_fine_grain_clk_vol()
840 if (hwmgr->hwmgr_func->set_fine_grain_clk_vol == NULL) in pp_set_fine_grain_clk_vol()
843 return hwmgr->hwmgr_func->set_fine_grain_clk_vol(hwmgr, type, input, size); in pp_set_fine_grain_clk_vol()
849 struct pp_hwmgr *hwmgr = handle; in pp_odn_edit_dpm_table() local
851 if (!hwmgr || !hwmgr->pm_en) in pp_odn_edit_dpm_table()
854 if (hwmgr->hwmgr_func->odn_edit_dpm_table == NULL) { in pp_odn_edit_dpm_table()
859 return hwmgr->hwmgr_func->odn_edit_dpm_table(hwmgr, type, input, size); in pp_odn_edit_dpm_table()
864 struct pp_hwmgr *hwmgr = handle; in pp_dpm_set_mp1_state() local
866 if (!hwmgr) in pp_dpm_set_mp1_state()
869 if (!hwmgr->pm_en) in pp_dpm_set_mp1_state()
872 if (hwmgr->hwmgr_func->set_mp1_state) in pp_dpm_set_mp1_state()
873 return hwmgr->hwmgr_func->set_mp1_state(hwmgr, mp1_state); in pp_dpm_set_mp1_state()
881 struct pp_hwmgr *hwmgr = handle; in pp_dpm_switch_power_profile() local
885 if (!hwmgr || !hwmgr->pm_en) in pp_dpm_switch_power_profile()
888 if (hwmgr->hwmgr_func->set_power_profile_mode == NULL) { in pp_dpm_switch_power_profile()
897 hwmgr->workload_mask &= ~(1 << hwmgr->workload_prority[type]); in pp_dpm_switch_power_profile()
898 index = fls(hwmgr->workload_mask); in pp_dpm_switch_power_profile()
900 workload = hwmgr->workload_setting[index]; in pp_dpm_switch_power_profile()
902 hwmgr->workload_mask |= (1 << hwmgr->workload_prority[type]); in pp_dpm_switch_power_profile()
903 index = fls(hwmgr->workload_mask); in pp_dpm_switch_power_profile()
905 workload = hwmgr->workload_setting[index]; in pp_dpm_switch_power_profile()
909 hwmgr->hwmgr_func->disable_power_features_for_compute_performance) { in pp_dpm_switch_power_profile()
910 if (hwmgr->hwmgr_func->disable_power_features_for_compute_performance(hwmgr, en)) in pp_dpm_switch_power_profile()
914 if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) in pp_dpm_switch_power_profile()
915 hwmgr->hwmgr_func->set_power_profile_mode(hwmgr, &workload, 0); in pp_dpm_switch_power_profile()
922 struct pp_hwmgr *hwmgr = handle; in pp_set_power_limit() local
925 if (!hwmgr || !hwmgr->pm_en) in pp_set_power_limit()
928 if (hwmgr->hwmgr_func->set_power_limit == NULL) { in pp_set_power_limit()
934 limit = hwmgr->default_power_limit; in pp_set_power_limit()
936 max_power_limit = hwmgr->default_power_limit; in pp_set_power_limit()
937 if (hwmgr->od_enabled) { in pp_set_power_limit()
938 max_power_limit *= (100 + hwmgr->platform_descriptor.TDPODLimit); in pp_set_power_limit()
945 hwmgr->hwmgr_func->set_power_limit(hwmgr, limit); in pp_set_power_limit()
946 hwmgr->power_limit = limit; in pp_set_power_limit()
954 struct pp_hwmgr *hwmgr = handle; in pp_get_power_limit() local
957 if (!hwmgr || !hwmgr->pm_en ||!limit) in pp_get_power_limit()
965 *limit = hwmgr->power_limit; in pp_get_power_limit()
968 *limit = hwmgr->default_power_limit; in pp_get_power_limit()
971 *limit = hwmgr->default_power_limit; in pp_get_power_limit()
972 if (hwmgr->od_enabled) { in pp_get_power_limit()
973 *limit *= (100 + hwmgr->platform_descriptor.TDPODLimit); in pp_get_power_limit()
988 struct pp_hwmgr *hwmgr = handle; in pp_display_configuration_change() local
990 if (!hwmgr || !hwmgr->pm_en) in pp_display_configuration_change()
993 phm_store_dal_configuration_data(hwmgr, display_config); in pp_display_configuration_change()
1000 struct pp_hwmgr *hwmgr = handle; in pp_get_display_power_level() local
1002 if (!hwmgr || !hwmgr->pm_en ||!output) in pp_get_display_power_level()
1005 return phm_get_dal_power_level(hwmgr, output); in pp_get_display_power_level()
1013 struct pp_hwmgr *hwmgr = handle; in pp_get_current_clocks() local
1016 if (!hwmgr || !hwmgr->pm_en) in pp_get_current_clocks()
1019 phm_get_dal_power_level(hwmgr, &simple_clocks); in pp_get_current_clocks()
1021 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, in pp_get_current_clocks()
1023 ret = phm_get_clock_info(hwmgr, &hwmgr->current_ps->hardware, in pp_get_current_clocks()
1026 ret = phm_get_clock_info(hwmgr, &hwmgr->current_ps->hardware, in pp_get_current_clocks()
1049 if (0 == phm_get_current_shallow_sleep_clocks(hwmgr, &hwmgr->current_ps->hardware, &hw_clocks)) { in pp_get_current_clocks()
1058 struct pp_hwmgr *hwmgr = handle; in pp_get_clock_by_type() local
1060 if (!hwmgr || !hwmgr->pm_en) in pp_get_clock_by_type()
1066 return phm_get_clock_by_type(hwmgr, type, clocks); in pp_get_clock_by_type()
1073 struct pp_hwmgr *hwmgr = handle; in pp_get_clock_by_type_with_latency() local
1075 if (!hwmgr || !hwmgr->pm_en ||!clocks) in pp_get_clock_by_type_with_latency()
1078 return phm_get_clock_by_type_with_latency(hwmgr, type, clocks); in pp_get_clock_by_type_with_latency()
1085 struct pp_hwmgr *hwmgr = handle; in pp_get_clock_by_type_with_voltage() local
1087 if (!hwmgr || !hwmgr->pm_en ||!clocks) in pp_get_clock_by_type_with_voltage()
1090 return phm_get_clock_by_type_with_voltage(hwmgr, type, clocks); in pp_get_clock_by_type_with_voltage()
1096 struct pp_hwmgr *hwmgr = handle; in pp_set_watermarks_for_clocks_ranges() local
1098 if (!hwmgr || !hwmgr->pm_en || !clock_ranges) in pp_set_watermarks_for_clocks_ranges()
1101 return phm_set_watermarks_for_clocks_ranges(hwmgr, in pp_set_watermarks_for_clocks_ranges()
1108 struct pp_hwmgr *hwmgr = handle; in pp_display_clock_voltage_request() local
1110 if (!hwmgr || !hwmgr->pm_en ||!clock) in pp_display_clock_voltage_request()
1113 return phm_display_clock_voltage_request(hwmgr, clock); in pp_display_clock_voltage_request()
1119 struct pp_hwmgr *hwmgr = handle; in pp_get_display_mode_validation_clocks() local
1122 if (!hwmgr || !hwmgr->pm_en ||!clocks) in pp_get_display_mode_validation_clocks()
1127 …if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DynamicPatchPowerSta… in pp_get_display_mode_validation_clocks()
1128 ret = phm_get_max_high_clocks(hwmgr, clocks); in pp_get_display_mode_validation_clocks()
1135 struct pp_hwmgr *hwmgr = handle; in pp_dpm_powergate_mmhub() local
1137 if (!hwmgr || !hwmgr->pm_en) in pp_dpm_powergate_mmhub()
1140 if (hwmgr->hwmgr_func->powergate_mmhub == NULL) { in pp_dpm_powergate_mmhub()
1145 return hwmgr->hwmgr_func->powergate_mmhub(hwmgr); in pp_dpm_powergate_mmhub()
1150 struct pp_hwmgr *hwmgr = handle; in pp_dpm_powergate_gfx() local
1152 if (!hwmgr || !hwmgr->pm_en) in pp_dpm_powergate_gfx()
1155 if (hwmgr->hwmgr_func->powergate_gfx == NULL) { in pp_dpm_powergate_gfx()
1160 return hwmgr->hwmgr_func->powergate_gfx(hwmgr, gate); in pp_dpm_powergate_gfx()
1165 struct pp_hwmgr *hwmgr = handle; in pp_dpm_powergate_acp() local
1167 if (!hwmgr || !hwmgr->pm_en) in pp_dpm_powergate_acp()
1170 if (hwmgr->hwmgr_func->powergate_acp == NULL) { in pp_dpm_powergate_acp()
1175 hwmgr->hwmgr_func->powergate_acp(hwmgr, gate); in pp_dpm_powergate_acp()
1180 struct pp_hwmgr *hwmgr = handle; in pp_dpm_powergate_sdma() local
1182 if (!hwmgr) in pp_dpm_powergate_sdma()
1185 if (hwmgr->hwmgr_func->powergate_sdma == NULL) { in pp_dpm_powergate_sdma()
1190 hwmgr->hwmgr_func->powergate_sdma(hwmgr, gate); in pp_dpm_powergate_sdma()
1231 struct pp_hwmgr *hwmgr = handle; in pp_notify_smu_enable_pwe() local
1233 if (!hwmgr || !hwmgr->pm_en) in pp_notify_smu_enable_pwe()
1236 if (hwmgr->hwmgr_func->smus_notify_pwe == NULL) { in pp_notify_smu_enable_pwe()
1241 hwmgr->hwmgr_func->smus_notify_pwe(hwmgr); in pp_notify_smu_enable_pwe()
1248 struct pp_hwmgr *hwmgr = handle; in pp_enable_mgpu_fan_boost() local
1250 if (!hwmgr) in pp_enable_mgpu_fan_boost()
1253 if (!hwmgr->pm_en || in pp_enable_mgpu_fan_boost()
1254 hwmgr->hwmgr_func->enable_mgpu_fan_boost == NULL) in pp_enable_mgpu_fan_boost()
1257 hwmgr->hwmgr_func->enable_mgpu_fan_boost(hwmgr); in pp_enable_mgpu_fan_boost()
1264 struct pp_hwmgr *hwmgr = handle; in pp_set_min_deep_sleep_dcefclk() local
1266 if (!hwmgr || !hwmgr->pm_en) in pp_set_min_deep_sleep_dcefclk()
1269 if (hwmgr->hwmgr_func->set_min_deep_sleep_dcefclk == NULL) { in pp_set_min_deep_sleep_dcefclk()
1274 hwmgr->hwmgr_func->set_min_deep_sleep_dcefclk(hwmgr, clock); in pp_set_min_deep_sleep_dcefclk()
1281 struct pp_hwmgr *hwmgr = handle; in pp_set_hard_min_dcefclk_by_freq() local
1283 if (!hwmgr || !hwmgr->pm_en) in pp_set_hard_min_dcefclk_by_freq()
1286 if (hwmgr->hwmgr_func->set_hard_min_dcefclk_by_freq == NULL) { in pp_set_hard_min_dcefclk_by_freq()
1291 hwmgr->hwmgr_func->set_hard_min_dcefclk_by_freq(hwmgr, clock); in pp_set_hard_min_dcefclk_by_freq()
1298 struct pp_hwmgr *hwmgr = handle; in pp_set_hard_min_fclk_by_freq() local
1300 if (!hwmgr || !hwmgr->pm_en) in pp_set_hard_min_fclk_by_freq()
1303 if (hwmgr->hwmgr_func->set_hard_min_fclk_by_freq == NULL) { in pp_set_hard_min_fclk_by_freq()
1308 hwmgr->hwmgr_func->set_hard_min_fclk_by_freq(hwmgr, clock); in pp_set_hard_min_fclk_by_freq()
1315 struct pp_hwmgr *hwmgr = handle; in pp_set_active_display_count() local
1317 if (!hwmgr || !hwmgr->pm_en) in pp_set_active_display_count()
1320 return phm_set_active_display_count(hwmgr, count); in pp_set_active_display_count()
1325 struct pp_hwmgr *hwmgr = handle; in pp_get_asic_baco_capability() local
1328 if (!hwmgr) in pp_get_asic_baco_capability()
1331 if (!(hwmgr->not_vf && amdgpu_dpm) || in pp_get_asic_baco_capability()
1332 !hwmgr->hwmgr_func->get_asic_baco_capability) in pp_get_asic_baco_capability()
1335 hwmgr->hwmgr_func->get_asic_baco_capability(hwmgr, cap); in pp_get_asic_baco_capability()
1342 struct pp_hwmgr *hwmgr = handle; in pp_get_asic_baco_state() local
1344 if (!hwmgr) in pp_get_asic_baco_state()
1347 if (!hwmgr->pm_en || !hwmgr->hwmgr_func->get_asic_baco_state) in pp_get_asic_baco_state()
1350 hwmgr->hwmgr_func->get_asic_baco_state(hwmgr, (enum BACO_STATE *)state); in pp_get_asic_baco_state()
1357 struct pp_hwmgr *hwmgr = handle; in pp_set_asic_baco_state() local
1359 if (!hwmgr) in pp_set_asic_baco_state()
1362 if (!(hwmgr->not_vf && amdgpu_dpm) || in pp_set_asic_baco_state()
1363 !hwmgr->hwmgr_func->set_asic_baco_state) in pp_set_asic_baco_state()
1366 hwmgr->hwmgr_func->set_asic_baco_state(hwmgr, (enum BACO_STATE)state); in pp_set_asic_baco_state()
1373 struct pp_hwmgr *hwmgr = handle; in pp_get_ppfeature_status() local
1375 if (!hwmgr || !hwmgr->pm_en || !buf) in pp_get_ppfeature_status()
1378 if (hwmgr->hwmgr_func->get_ppfeature_status == NULL) { in pp_get_ppfeature_status()
1383 return hwmgr->hwmgr_func->get_ppfeature_status(hwmgr, buf); in pp_get_ppfeature_status()
1388 struct pp_hwmgr *hwmgr = handle; in pp_set_ppfeature_status() local
1390 if (!hwmgr || !hwmgr->pm_en) in pp_set_ppfeature_status()
1393 if (hwmgr->hwmgr_func->set_ppfeature_status == NULL) { in pp_set_ppfeature_status()
1398 return hwmgr->hwmgr_func->set_ppfeature_status(hwmgr, ppfeature_masks); in pp_set_ppfeature_status()
1403 struct pp_hwmgr *hwmgr = handle; in pp_asic_reset_mode_2() local
1405 if (!hwmgr || !hwmgr->pm_en) in pp_asic_reset_mode_2()
1408 if (hwmgr->hwmgr_func->asic_reset == NULL) { in pp_asic_reset_mode_2()
1413 return hwmgr->hwmgr_func->asic_reset(hwmgr, SMU_ASIC_RESET_MODE_2); in pp_asic_reset_mode_2()
1418 struct pp_hwmgr *hwmgr = handle; in pp_smu_i2c_bus_access() local
1420 if (!hwmgr || !hwmgr->pm_en) in pp_smu_i2c_bus_access()
1423 if (hwmgr->hwmgr_func->smu_i2c_bus_access == NULL) { in pp_smu_i2c_bus_access()
1428 return hwmgr->hwmgr_func->smu_i2c_bus_access(hwmgr, acquire); in pp_smu_i2c_bus_access()
1433 struct pp_hwmgr *hwmgr = handle; in pp_set_df_cstate() local
1435 if (!hwmgr) in pp_set_df_cstate()
1438 if (!hwmgr->pm_en || !hwmgr->hwmgr_func->set_df_cstate) in pp_set_df_cstate()
1441 hwmgr->hwmgr_func->set_df_cstate(hwmgr, state); in pp_set_df_cstate()
1448 struct pp_hwmgr *hwmgr = handle; in pp_set_xgmi_pstate() local
1450 if (!hwmgr) in pp_set_xgmi_pstate()
1453 if (!hwmgr->pm_en || !hwmgr->hwmgr_func->set_xgmi_pstate) in pp_set_xgmi_pstate()
1456 hwmgr->hwmgr_func->set_xgmi_pstate(hwmgr, pstate); in pp_set_xgmi_pstate()
1463 struct pp_hwmgr *hwmgr = handle; in pp_get_gpu_metrics() local
1465 if (!hwmgr) in pp_get_gpu_metrics()
1468 if (!hwmgr->pm_en || !hwmgr->hwmgr_func->get_gpu_metrics) in pp_get_gpu_metrics()
1471 return hwmgr->hwmgr_func->get_gpu_metrics(hwmgr, table); in pp_get_gpu_metrics()
1476 struct pp_hwmgr *hwmgr = handle; in pp_gfx_state_change_set() local
1478 if (!hwmgr || !hwmgr->pm_en) in pp_gfx_state_change_set()
1481 if (hwmgr->hwmgr_func->gfx_state_change == NULL) { in pp_gfx_state_change_set()
1486 hwmgr->hwmgr_func->gfx_state_change(hwmgr, state); in pp_gfx_state_change_set()
1492 struct pp_hwmgr *hwmgr = handle; in pp_get_prv_buffer_details() local
1493 struct amdgpu_device *adev = hwmgr->adev; in pp_get_prv_buffer_details()
1513 struct pp_hwmgr *hwmgr = handle; in pp_pm_compute_clocks() local
1514 struct amdgpu_device *adev = hwmgr->adev; in pp_pm_compute_clocks()