Lines Matching refs:hwmgr
50 extern int smu10_init_function_pointers(struct pp_hwmgr *hwmgr);
52 static int polaris_set_asic_special_caps(struct pp_hwmgr *hwmgr);
53 static void hwmgr_init_default_caps(struct pp_hwmgr *hwmgr);
54 static int hwmgr_set_user_specify_caps(struct pp_hwmgr *hwmgr);
55 static int fiji_set_asic_special_caps(struct pp_hwmgr *hwmgr);
56 static int tonga_set_asic_special_caps(struct pp_hwmgr *hwmgr);
57 static int topaz_set_asic_special_caps(struct pp_hwmgr *hwmgr);
58 static int ci_set_asic_special_caps(struct pp_hwmgr *hwmgr);
61 static void hwmgr_init_workload_prority(struct pp_hwmgr *hwmgr) in hwmgr_init_workload_prority() argument
63 hwmgr->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = 0; in hwmgr_init_workload_prority()
64 hwmgr->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 1; in hwmgr_init_workload_prority()
65 hwmgr->workload_prority[PP_SMC_POWER_PROFILE_POWERSAVING] = 2; in hwmgr_init_workload_prority()
66 hwmgr->workload_prority[PP_SMC_POWER_PROFILE_VIDEO] = 3; in hwmgr_init_workload_prority()
67 hwmgr->workload_prority[PP_SMC_POWER_PROFILE_VR] = 4; in hwmgr_init_workload_prority()
68 hwmgr->workload_prority[PP_SMC_POWER_PROFILE_COMPUTE] = 5; in hwmgr_init_workload_prority()
70 hwmgr->workload_setting[0] = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; in hwmgr_init_workload_prority()
71 hwmgr->workload_setting[1] = PP_SMC_POWER_PROFILE_FULLSCREEN3D; in hwmgr_init_workload_prority()
72 hwmgr->workload_setting[2] = PP_SMC_POWER_PROFILE_POWERSAVING; in hwmgr_init_workload_prority()
73 hwmgr->workload_setting[3] = PP_SMC_POWER_PROFILE_VIDEO; in hwmgr_init_workload_prority()
74 hwmgr->workload_setting[4] = PP_SMC_POWER_PROFILE_VR; in hwmgr_init_workload_prority()
75 hwmgr->workload_setting[5] = PP_SMC_POWER_PROFILE_COMPUTE; in hwmgr_init_workload_prority()
78 int hwmgr_early_init(struct pp_hwmgr *hwmgr) in hwmgr_early_init() argument
82 if (!hwmgr) in hwmgr_early_init()
85 hwmgr->usec_timeout = AMD_MAX_USEC_TIMEOUT; in hwmgr_early_init()
86 hwmgr->pp_table_version = PP_TABLE_V1; in hwmgr_early_init()
87 hwmgr->dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; in hwmgr_early_init()
88 hwmgr->request_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; in hwmgr_early_init()
89 hwmgr_init_default_caps(hwmgr); in hwmgr_early_init()
90 hwmgr_set_user_specify_caps(hwmgr); in hwmgr_early_init()
91 hwmgr->fan_ctrl_is_in_default_mode = true; in hwmgr_early_init()
92 hwmgr_init_workload_prority(hwmgr); in hwmgr_early_init()
93 hwmgr->gfxoff_state_changed_by_workload = false; in hwmgr_early_init()
95 adev = hwmgr->adev; in hwmgr_early_init()
97 switch (hwmgr->chip_family) { in hwmgr_early_init()
100 hwmgr->smumgr_funcs = &ci_smu_funcs; in hwmgr_early_init()
101 ci_set_asic_special_caps(hwmgr); in hwmgr_early_init()
102 hwmgr->feature_mask &= ~(PP_VBI_TIME_SUPPORT_MASK | in hwmgr_early_init()
105 hwmgr->pp_table_version = PP_TABLE_V0; in hwmgr_early_init()
106 hwmgr->od_enabled = false; in hwmgr_early_init()
107 smu7_init_function_pointers(hwmgr); in hwmgr_early_init()
111 hwmgr->od_enabled = false; in hwmgr_early_init()
112 hwmgr->smumgr_funcs = &smu8_smu_funcs; in hwmgr_early_init()
113 hwmgr->feature_mask &= ~PP_GFXOFF_MASK; in hwmgr_early_init()
114 smu8_init_function_pointers(hwmgr); in hwmgr_early_init()
118 hwmgr->feature_mask &= ~PP_GFXOFF_MASK; in hwmgr_early_init()
119 switch (hwmgr->chip_id) { in hwmgr_early_init()
121 hwmgr->smumgr_funcs = &iceland_smu_funcs; in hwmgr_early_init()
122 topaz_set_asic_special_caps(hwmgr); in hwmgr_early_init()
123 hwmgr->feature_mask &= ~ (PP_VBI_TIME_SUPPORT_MASK | in hwmgr_early_init()
125 hwmgr->pp_table_version = PP_TABLE_V0; in hwmgr_early_init()
126 hwmgr->od_enabled = false; in hwmgr_early_init()
129 hwmgr->smumgr_funcs = &tonga_smu_funcs; in hwmgr_early_init()
130 tonga_set_asic_special_caps(hwmgr); in hwmgr_early_init()
131 hwmgr->feature_mask &= ~PP_VBI_TIME_SUPPORT_MASK; in hwmgr_early_init()
134 hwmgr->smumgr_funcs = &fiji_smu_funcs; in hwmgr_early_init()
135 fiji_set_asic_special_caps(hwmgr); in hwmgr_early_init()
136 hwmgr->feature_mask &= ~ (PP_VBI_TIME_SUPPORT_MASK | in hwmgr_early_init()
142 hwmgr->smumgr_funcs = &polaris10_smu_funcs; in hwmgr_early_init()
143 polaris_set_asic_special_caps(hwmgr); in hwmgr_early_init()
144 hwmgr->feature_mask &= ~(PP_UVD_HANDSHAKE_MASK); in hwmgr_early_init()
147 hwmgr->smumgr_funcs = &vegam_smu_funcs; in hwmgr_early_init()
148 polaris_set_asic_special_caps(hwmgr); in hwmgr_early_init()
149 hwmgr->feature_mask &= ~(PP_UVD_HANDSHAKE_MASK); in hwmgr_early_init()
154 smu7_init_function_pointers(hwmgr); in hwmgr_early_init()
157 switch (hwmgr->chip_id) { in hwmgr_early_init()
160 hwmgr->feature_mask &= ~PP_GFXOFF_MASK; in hwmgr_early_init()
161 hwmgr->smumgr_funcs = &vega10_smu_funcs; in hwmgr_early_init()
162 vega10_hwmgr_init(hwmgr); in hwmgr_early_init()
165 hwmgr->smumgr_funcs = &vega12_smu_funcs; in hwmgr_early_init()
166 vega12_hwmgr_init(hwmgr); in hwmgr_early_init()
170 hwmgr->feature_mask &= ~PP_GFXOFF_MASK; in hwmgr_early_init()
171 hwmgr->smumgr_funcs = &vega20_smu_funcs; in hwmgr_early_init()
172 vega20_hwmgr_init(hwmgr); in hwmgr_early_init()
179 switch (hwmgr->chip_id) { in hwmgr_early_init()
181 hwmgr->od_enabled = false; in hwmgr_early_init()
182 hwmgr->smumgr_funcs = &smu10_smu_funcs; in hwmgr_early_init()
183 smu10_init_function_pointers(hwmgr); in hwmgr_early_init()
196 int hwmgr_sw_init(struct pp_hwmgr *hwmgr) in hwmgr_sw_init() argument
198 if (!hwmgr|| !hwmgr->smumgr_funcs || !hwmgr->smumgr_funcs->smu_init) in hwmgr_sw_init()
201 phm_register_irq_handlers(hwmgr); in hwmgr_sw_init()
202 pr_info("hwmgr_sw_init smu backed is %s\n", hwmgr->smumgr_funcs->name); in hwmgr_sw_init()
204 return hwmgr->smumgr_funcs->smu_init(hwmgr); in hwmgr_sw_init()
208 int hwmgr_sw_fini(struct pp_hwmgr *hwmgr) in hwmgr_sw_fini() argument
210 if (hwmgr && hwmgr->smumgr_funcs && hwmgr->smumgr_funcs->smu_fini) in hwmgr_sw_fini()
211 hwmgr->smumgr_funcs->smu_fini(hwmgr); in hwmgr_sw_fini()
216 int hwmgr_hw_init(struct pp_hwmgr *hwmgr) in hwmgr_hw_init() argument
220 hwmgr->pp_one_vf = amdgpu_sriov_is_pp_one_vf((struct amdgpu_device *)hwmgr->adev); in hwmgr_hw_init()
221 hwmgr->pm_en = (amdgpu_dpm && (hwmgr->not_vf || hwmgr->pp_one_vf)) in hwmgr_hw_init()
223 if (!hwmgr->pm_en) in hwmgr_hw_init()
226 if (!hwmgr->pptable_func || in hwmgr_hw_init()
227 !hwmgr->pptable_func->pptable_init || in hwmgr_hw_init()
228 !hwmgr->hwmgr_func->backend_init) { in hwmgr_hw_init()
229 hwmgr->pm_en = false; in hwmgr_hw_init()
234 ret = hwmgr->pptable_func->pptable_init(hwmgr); in hwmgr_hw_init()
238 ((struct amdgpu_device *)hwmgr->adev)->pm.no_fan = in hwmgr_hw_init()
239 hwmgr->thermal_controller.fanInfo.bNoFan; in hwmgr_hw_init()
241 ret = hwmgr->hwmgr_func->backend_init(hwmgr); in hwmgr_hw_init()
245 if ((hwmgr->dyn_state.max_clock_voltage_on_dc.sclk == 0) || in hwmgr_hw_init()
246 (hwmgr->dyn_state.max_clock_voltage_on_dc.mclk == 0)) in hwmgr_hw_init()
247 hwmgr->dyn_state.max_clock_voltage_on_dc = in hwmgr_hw_init()
248 hwmgr->dyn_state.max_clock_voltage_on_ac; in hwmgr_hw_init()
250 ret = psm_init_power_state_table(hwmgr); in hwmgr_hw_init()
254 ret = phm_setup_asic(hwmgr); in hwmgr_hw_init()
258 ret = phm_enable_dynamic_state_management(hwmgr); in hwmgr_hw_init()
261 ret = phm_start_thermal_controller(hwmgr); in hwmgr_hw_init()
262 ret |= psm_set_performance_states(hwmgr); in hwmgr_hw_init()
266 ((struct amdgpu_device *)hwmgr->adev)->pm.dpm_enabled = true; in hwmgr_hw_init()
270 if (hwmgr->hwmgr_func->backend_fini) in hwmgr_hw_init()
271 hwmgr->hwmgr_func->backend_fini(hwmgr); in hwmgr_hw_init()
273 if (hwmgr->pptable_func->pptable_fini) in hwmgr_hw_init()
274 hwmgr->pptable_func->pptable_fini(hwmgr); in hwmgr_hw_init()
279 int hwmgr_hw_fini(struct pp_hwmgr *hwmgr) in hwmgr_hw_fini() argument
281 if (!hwmgr || !hwmgr->pm_en || !hwmgr->not_vf) in hwmgr_hw_fini()
284 phm_stop_thermal_controller(hwmgr); in hwmgr_hw_fini()
285 psm_set_boot_states(hwmgr); in hwmgr_hw_fini()
286 psm_adjust_power_state_dynamic(hwmgr, true, NULL); in hwmgr_hw_fini()
287 phm_disable_dynamic_state_management(hwmgr); in hwmgr_hw_fini()
288 phm_disable_clock_power_gatings(hwmgr); in hwmgr_hw_fini()
290 if (hwmgr->hwmgr_func->backend_fini) in hwmgr_hw_fini()
291 hwmgr->hwmgr_func->backend_fini(hwmgr); in hwmgr_hw_fini()
292 if (hwmgr->pptable_func->pptable_fini) in hwmgr_hw_fini()
293 hwmgr->pptable_func->pptable_fini(hwmgr); in hwmgr_hw_fini()
294 return psm_fini_power_state_table(hwmgr); in hwmgr_hw_fini()
297 int hwmgr_suspend(struct pp_hwmgr *hwmgr) in hwmgr_suspend() argument
301 if (!hwmgr || !hwmgr->pm_en || !hwmgr->not_vf) in hwmgr_suspend()
304 phm_disable_smc_firmware_ctf(hwmgr); in hwmgr_suspend()
305 ret = psm_set_boot_states(hwmgr); in hwmgr_suspend()
308 ret = psm_adjust_power_state_dynamic(hwmgr, true, NULL); in hwmgr_suspend()
311 ret = phm_power_down_asic(hwmgr); in hwmgr_suspend()
316 int hwmgr_resume(struct pp_hwmgr *hwmgr) in hwmgr_resume() argument
320 if (!hwmgr) in hwmgr_resume()
323 if (!hwmgr->not_vf || !hwmgr->pm_en) in hwmgr_resume()
326 ret = phm_setup_asic(hwmgr); in hwmgr_resume()
330 ret = phm_enable_dynamic_state_management(hwmgr); in hwmgr_resume()
333 ret = phm_start_thermal_controller(hwmgr); in hwmgr_resume()
334 ret |= psm_set_performance_states(hwmgr); in hwmgr_resume()
338 ret = psm_adjust_power_state_dynamic(hwmgr, false, NULL); in hwmgr_resume()
357 int hwmgr_handle_task(struct pp_hwmgr *hwmgr, enum amd_pp_task task_id, in hwmgr_handle_task() argument
362 if (hwmgr == NULL) in hwmgr_handle_task()
367 if (!hwmgr->not_vf) in hwmgr_handle_task()
369 ret = phm_pre_display_configuration_changed(hwmgr); in hwmgr_handle_task()
372 ret = phm_set_cpu_power_state(hwmgr); in hwmgr_handle_task()
375 ret = psm_set_performance_states(hwmgr); in hwmgr_handle_task()
378 ret = psm_adjust_power_state_dynamic(hwmgr, false, NULL); in hwmgr_handle_task()
385 if (!hwmgr->not_vf) in hwmgr_handle_task()
393 ret = psm_set_user_performance_state(hwmgr, requested_ui_label, &requested_ps); in hwmgr_handle_task()
396 ret = psm_adjust_power_state_dynamic(hwmgr, true, requested_ps); in hwmgr_handle_task()
401 ret = psm_adjust_power_state_dynamic(hwmgr, true, NULL); in hwmgr_handle_task()
409 void hwmgr_init_default_caps(struct pp_hwmgr *hwmgr) in hwmgr_init_default_caps() argument
411 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PCIEPerformanceRequest); in hwmgr_init_default_caps()
413 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_UVDDPM); in hwmgr_init_default_caps()
414 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_VCEDPM); in hwmgr_init_default_caps()
417 if (amdgpu_acpi_is_pcie_performance_request_supported(hwmgr->adev)) in hwmgr_init_default_caps()
418 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PCIEPerformanceRequest); in hwmgr_init_default_caps()
421 phm_cap_set(hwmgr->platform_descriptor.platformCaps, in hwmgr_init_default_caps()
424 phm_cap_set(hwmgr->platform_descriptor.platformCaps, in hwmgr_init_default_caps()
427 phm_cap_set(hwmgr->platform_descriptor.platformCaps, in hwmgr_init_default_caps()
430 phm_cap_set(hwmgr->platform_descriptor.platformCaps, in hwmgr_init_default_caps()
433 phm_cap_set(hwmgr->platform_descriptor.platformCaps, in hwmgr_init_default_caps()
436 phm_cap_set(hwmgr->platform_descriptor.platformCaps, in hwmgr_init_default_caps()
441 int hwmgr_set_user_specify_caps(struct pp_hwmgr *hwmgr) in hwmgr_set_user_specify_caps() argument
443 if (hwmgr->feature_mask & PP_SCLK_DEEP_SLEEP_MASK) in hwmgr_set_user_specify_caps()
444 phm_cap_set(hwmgr->platform_descriptor.platformCaps, in hwmgr_set_user_specify_caps()
447 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, in hwmgr_set_user_specify_caps()
450 if (hwmgr->feature_mask & PP_POWER_CONTAINMENT_MASK) { in hwmgr_set_user_specify_caps()
451 phm_cap_set(hwmgr->platform_descriptor.platformCaps, in hwmgr_set_user_specify_caps()
453 phm_cap_set(hwmgr->platform_descriptor.platformCaps, in hwmgr_set_user_specify_caps()
456 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, in hwmgr_set_user_specify_caps()
458 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, in hwmgr_set_user_specify_caps()
462 if (hwmgr->feature_mask & PP_OVERDRIVE_MASK) in hwmgr_set_user_specify_caps()
463 hwmgr->od_enabled = true; in hwmgr_set_user_specify_caps()
468 int polaris_set_asic_special_caps(struct pp_hwmgr *hwmgr) in polaris_set_asic_special_caps() argument
470 phm_cap_set(hwmgr->platform_descriptor.platformCaps, in polaris_set_asic_special_caps()
472 phm_cap_set(hwmgr->platform_descriptor.platformCaps, in polaris_set_asic_special_caps()
474 phm_cap_set(hwmgr->platform_descriptor.platformCaps, in polaris_set_asic_special_caps()
477 phm_cap_set(hwmgr->platform_descriptor.platformCaps, in polaris_set_asic_special_caps()
479 phm_cap_set(hwmgr->platform_descriptor.platformCaps, in polaris_set_asic_special_caps()
482 phm_cap_set(hwmgr->platform_descriptor.platformCaps, in polaris_set_asic_special_caps()
485 if (((hwmgr->chip_id == CHIP_POLARIS11) && !hwmgr->is_kicker) || in polaris_set_asic_special_caps()
486 (hwmgr->chip_id == CHIP_POLARIS12)) in polaris_set_asic_special_caps()
487 phm_cap_set(hwmgr->platform_descriptor.platformCaps, in polaris_set_asic_special_caps()
490 if (hwmgr->chip_id != CHIP_POLARIS11) { in polaris_set_asic_special_caps()
491 phm_cap_set(hwmgr->platform_descriptor.platformCaps, in polaris_set_asic_special_caps()
493 phm_cap_set(hwmgr->platform_descriptor.platformCaps, in polaris_set_asic_special_caps()
495 phm_cap_set(hwmgr->platform_descriptor.platformCaps, in polaris_set_asic_special_caps()
501 int fiji_set_asic_special_caps(struct pp_hwmgr *hwmgr) in fiji_set_asic_special_caps() argument
503 phm_cap_set(hwmgr->platform_descriptor.platformCaps, in fiji_set_asic_special_caps()
505 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, in fiji_set_asic_special_caps()
507 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, in fiji_set_asic_special_caps()
509 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, in fiji_set_asic_special_caps()
511 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, in fiji_set_asic_special_caps()
516 int tonga_set_asic_special_caps(struct pp_hwmgr *hwmgr) in tonga_set_asic_special_caps() argument
518 phm_cap_set(hwmgr->platform_descriptor.platformCaps, in tonga_set_asic_special_caps()
520 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, in tonga_set_asic_special_caps()
522 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, in tonga_set_asic_special_caps()
524 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, in tonga_set_asic_special_caps()
526 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, in tonga_set_asic_special_caps()
529 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, in tonga_set_asic_special_caps()
531 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, in tonga_set_asic_special_caps()
536 int topaz_set_asic_special_caps(struct pp_hwmgr *hwmgr) in topaz_set_asic_special_caps() argument
538 phm_cap_set(hwmgr->platform_descriptor.platformCaps, in topaz_set_asic_special_caps()
540 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, in topaz_set_asic_special_caps()
542 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, in topaz_set_asic_special_caps()
544 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, in topaz_set_asic_special_caps()
546 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, in topaz_set_asic_special_caps()
551 int ci_set_asic_special_caps(struct pp_hwmgr *hwmgr) in ci_set_asic_special_caps() argument
553 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, in ci_set_asic_special_caps()
555 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, in ci_set_asic_special_caps()
557 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, in ci_set_asic_special_caps()
559 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, in ci_set_asic_special_caps()
561 phm_cap_set(hwmgr->platform_descriptor.platformCaps, in ci_set_asic_special_caps()
563 phm_cap_set(hwmgr->platform_descriptor.platformCaps, in ci_set_asic_special_caps()