Lines Matching refs:hwmgr
50 static uint16_t get_vce_table_offset(struct pp_hwmgr *hwmgr, in get_vce_table_offset() argument
74 static uint16_t get_vce_clock_info_array_offset(struct pp_hwmgr *hwmgr, in get_vce_clock_info_array_offset() argument
77 uint16_t table_offset = get_vce_table_offset(hwmgr, in get_vce_clock_info_array_offset()
86 static uint16_t get_vce_clock_info_array_size(struct pp_hwmgr *hwmgr, in get_vce_clock_info_array_size() argument
89 uint16_t table_offset = get_vce_clock_info_array_offset(hwmgr, in get_vce_clock_info_array_size()
102 static uint16_t get_vce_clock_voltage_limit_table_offset(struct pp_hwmgr *hwmgr, in get_vce_clock_voltage_limit_table_offset() argument
105 uint16_t table_offset = get_vce_clock_info_array_offset(hwmgr, in get_vce_clock_voltage_limit_table_offset()
109 return table_offset + get_vce_clock_info_array_size(hwmgr, in get_vce_clock_voltage_limit_table_offset()
115 static uint16_t get_vce_clock_voltage_limit_table_size(struct pp_hwmgr *hwmgr, in get_vce_clock_voltage_limit_table_size() argument
118 uint16_t table_offset = get_vce_clock_voltage_limit_table_offset(hwmgr, powerplay_table); in get_vce_clock_voltage_limit_table_size()
130 static uint16_t get_vce_state_table_offset(struct pp_hwmgr *hwmgr, const ATOM_PPLIB_POWERPLAYTABLE … in get_vce_state_table_offset() argument
132 uint16_t table_offset = get_vce_clock_voltage_limit_table_offset(hwmgr, powerplay_table); in get_vce_state_table_offset()
135 return table_offset + get_vce_clock_voltage_limit_table_size(hwmgr, powerplay_table); in get_vce_state_table_offset()
141 struct pp_hwmgr *hwmgr, in get_vce_state_table() argument
144 uint16_t table_offset = get_vce_state_table_offset(hwmgr, powerplay_table); in get_vce_state_table()
152 static uint16_t get_uvd_table_offset(struct pp_hwmgr *hwmgr, in get_uvd_table_offset() argument
174 static uint16_t get_uvd_clock_info_array_offset(struct pp_hwmgr *hwmgr, in get_uvd_clock_info_array_offset() argument
177 uint16_t table_offset = get_uvd_table_offset(hwmgr, in get_uvd_clock_info_array_offset()
185 static uint16_t get_uvd_clock_info_array_size(struct pp_hwmgr *hwmgr, in get_uvd_clock_info_array_size() argument
188 uint16_t table_offset = get_uvd_clock_info_array_offset(hwmgr, in get_uvd_clock_info_array_size()
204 struct pp_hwmgr *hwmgr, in get_uvd_clock_voltage_limit_table_offset() argument
207 uint16_t table_offset = get_uvd_clock_info_array_offset(hwmgr, in get_uvd_clock_voltage_limit_table_offset()
212 get_uvd_clock_info_array_size(hwmgr, powerplay_table); in get_uvd_clock_voltage_limit_table_offset()
217 static uint16_t get_samu_table_offset(struct pp_hwmgr *hwmgr, in get_samu_table_offset() argument
241 struct pp_hwmgr *hwmgr, in get_samu_clock_voltage_limit_table_offset() argument
244 uint16_t table_offset = get_samu_table_offset(hwmgr, in get_samu_clock_voltage_limit_table_offset()
253 static uint16_t get_acp_table_offset(struct pp_hwmgr *hwmgr, in get_acp_table_offset() argument
277 struct pp_hwmgr *hwmgr, in get_acp_clock_voltage_limit_table_offset() argument
280 uint16_t tableOffset = get_acp_table_offset(hwmgr, powerplay_table); in get_acp_clock_voltage_limit_table_offset()
289 struct pp_hwmgr *hwmgr, in get_cacp_tdp_table_offset() argument
312 static int get_cac_tdp_table(struct pp_hwmgr *hwmgr, in get_cac_tdp_table() argument
340 static uint16_t get_sclk_vdd_gfx_table_offset(struct pp_hwmgr *hwmgr, in get_sclk_vdd_gfx_table_offset() argument
365 struct pp_hwmgr *hwmgr, in get_sclk_vdd_gfx_clock_voltage_dependency_table_offset() argument
368 uint16_t tableOffset = get_sclk_vdd_gfx_table_offset(hwmgr, powerplay_table); in get_sclk_vdd_gfx_clock_voltage_dependency_table_offset()
377 static int get_clock_voltage_dependency_table(struct pp_hwmgr *hwmgr, in get_clock_voltage_dependency_table() argument
405 static int get_valid_clk(struct pp_hwmgr *hwmgr, in get_valid_clk() argument
426 static int get_clock_voltage_limit(struct pp_hwmgr *hwmgr, in get_clock_voltage_limit() argument
441 static void set_hw_cap(struct pp_hwmgr *hwmgr, bool enable, in set_hw_cap() argument
445 phm_cap_set(hwmgr->platform_descriptor.platformCaps, cap); in set_hw_cap()
447 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, cap); in set_hw_cap()
450 static int set_platform_caps(struct pp_hwmgr *hwmgr, in set_platform_caps() argument
454 hwmgr, in set_platform_caps()
460 hwmgr, in set_platform_caps()
466 hwmgr, in set_platform_caps()
472 hwmgr, in set_platform_caps()
478 hwmgr, in set_platform_caps()
484 hwmgr, in set_platform_caps()
490 hwmgr, in set_platform_caps()
496 hwmgr, in set_platform_caps()
502 hwmgr, in set_platform_caps()
508 hwmgr, in set_platform_caps()
514 hwmgr, in set_platform_caps()
520 hwmgr, in set_platform_caps()
526 hwmgr, in set_platform_caps()
532 hwmgr, in set_platform_caps()
538 hwmgr, in set_platform_caps()
544 hwmgr, in set_platform_caps()
550 hwmgr, in set_platform_caps()
556 hwmgr, in set_platform_caps()
562 hwmgr, in set_platform_caps()
568 hwmgr, in set_platform_caps()
574 hwmgr, in set_platform_caps()
580 hwmgr, in set_platform_caps()
586 hwmgr, in set_platform_caps()
592 hwmgr, in set_platform_caps()
598 hwmgr, in set_platform_caps()
604 hwmgr, in set_platform_caps()
610 hwmgr, in set_platform_caps()
619 struct pp_hwmgr *hwmgr, in make_classification_flags() argument
676 static int init_non_clock_fields(struct pp_hwmgr *hwmgr, in init_non_clock_fields() argument
685 ps->classification.flags = make_classification_flags(hwmgr, in init_non_clock_fields()
826 struct pp_hwmgr *hwmgr) in get_powerplay_table() argument
828 const void *table_addr = hwmgr->soft_pp_table; in get_powerplay_table()
833 if (hwmgr->chip_id == CHIP_RAVEN) { in get_powerplay_table()
835 hwmgr->soft_pp_table = &soft_dummy_pp_table[0]; in get_powerplay_table()
836 hwmgr->soft_pp_table_size = sizeof(soft_dummy_pp_table); in get_powerplay_table()
838 table_addr = smu_atom_get_data_table(hwmgr->adev, in get_powerplay_table()
841 hwmgr->soft_pp_table = table_addr; in get_powerplay_table()
842 hwmgr->soft_pp_table_size = size; in get_powerplay_table()
849 int pp_tables_get_response_times(struct pp_hwmgr *hwmgr, in pp_tables_get_response_times() argument
852 const ATOM_PPLIB_POWERPLAYTABLE *powerplay_tab = get_powerplay_table(hwmgr); in pp_tables_get_response_times()
863 int pp_tables_get_num_of_entries(struct pp_hwmgr *hwmgr, in pp_tables_get_num_of_entries() argument
867 const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table = get_powerplay_table(hwmgr); in pp_tables_get_num_of_entries()
883 int pp_tables_get_entry(struct pp_hwmgr *hwmgr, in pp_tables_get_entry() argument
892 const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table = get_powerplay_table(hwmgr); in pp_tables_get_entry()
924 result = init_non_clock_fields(hwmgr, ps, pnon_clock_arrays->ucEntrySize, pnon_clock_info); in pp_tables_get_entry()
930 res = func(hwmgr, &ps->hardware, i, pclock_info); in pp_tables_get_entry()
947 result = init_non_clock_fields(hwmgr, ps, in pp_tables_get_entry()
957 int res = func(hwmgr, &ps->hardware, i, pclock_info); in pp_tables_get_entry()
965 if (hwmgr->chip_family < AMDGPU_FAMILY_RV) in pp_tables_get_entry()
966 result = hwmgr->hwmgr_func->patch_boot_state(hwmgr, &(ps->hardware)); in pp_tables_get_entry()
973 struct pp_hwmgr *hwmgr, in init_powerplay_tables() argument
982 struct pp_hwmgr *hwmgr, in init_thermal_controller() argument
985 struct amdgpu_device *adev = hwmgr->adev; in init_thermal_controller()
987 hwmgr->thermal_controller.ucType = in init_thermal_controller()
989 hwmgr->thermal_controller.ucI2cLine = in init_thermal_controller()
991 hwmgr->thermal_controller.ucI2cAddress = in init_thermal_controller()
994 hwmgr->thermal_controller.fanInfo.bNoFan = in init_thermal_controller()
998 hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution = in init_thermal_controller()
1002 hwmgr->thermal_controller.fanInfo.ulMinRPM in init_thermal_controller()
1004 hwmgr->thermal_controller.fanInfo.ulMaxRPM in init_thermal_controller()
1007 set_hw_cap(hwmgr, in init_thermal_controller()
1008 ATOM_PP_THERMALCONTROLLER_NONE != hwmgr->thermal_controller.ucType, in init_thermal_controller()
1016 hwmgr->thermal_controller.use_hw_fan_control = 1; in init_thermal_controller()
1024 hwmgr->thermal_controller.advanceFanControlParameters.ucTHyst = in init_thermal_controller()
1026 hwmgr->thermal_controller.advanceFanControlParameters.usTMin = in init_thermal_controller()
1028 hwmgr->thermal_controller.advanceFanControlParameters.usTMed = in init_thermal_controller()
1030 hwmgr->thermal_controller.advanceFanControlParameters.usTHigh = in init_thermal_controller()
1032 hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin = in init_thermal_controller()
1034 hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed = in init_thermal_controller()
1036 hwmgr->thermal_controller.advanceFanControlParameters.usPWMHigh = in init_thermal_controller()
1038 hwmgr->thermal_controller.advanceFanControlParameters.usTMax = 10900; in init_thermal_controller()
1039 hwmgr->thermal_controller.advanceFanControlParameters.ulCycleDelay = 100000; in init_thermal_controller()
1041 phm_cap_set(hwmgr->platform_descriptor.platformCaps, in init_thermal_controller()
1049 hwmgr->thermal_controller.advanceFanControlParameters.usTMax = in init_thermal_controller()
1058 hwmgr->thermal_controller.advanceFanControlParameters.ucFanControlMode = in init_thermal_controller()
1063 hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanPWM = in init_thermal_controller()
1066 hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanPWM = in init_thermal_controller()
1069 hwmgr->thermal_controller.advanceFanControlParameters.usDefaultFanOutputSensitivity = in init_thermal_controller()
1071 hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity = in init_thermal_controller()
1080 phm_cap_set(hwmgr->platform_descriptor.platformCaps, in init_thermal_controller()
1083 hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanRPM = in init_thermal_controller()
1095 phm_cap_set(hwmgr->platform_descriptor.platformCaps, in init_thermal_controller()
1097 hwmgr->thermal_controller.advanceFanControlParameters.usFanCurrentLow = in init_thermal_controller()
1099 hwmgr->thermal_controller.advanceFanControlParameters.usFanCurrentHigh = in init_thermal_controller()
1101 hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMLow = in init_thermal_controller()
1103 hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMHigh = in init_thermal_controller()
1113 static int init_overdrive_limits_V1_4(struct pp_hwmgr *hwmgr, in init_overdrive_limits_V1_4() argument
1117 hwmgr->platform_descriptor.overdriveLimit.engineClock = in init_overdrive_limits_V1_4()
1120 hwmgr->platform_descriptor.overdriveLimit.memoryClock = in init_overdrive_limits_V1_4()
1123 hwmgr->platform_descriptor.maxOverdriveVDDC = in init_overdrive_limits_V1_4()
1126 hwmgr->platform_descriptor.minOverdriveVDDC = in init_overdrive_limits_V1_4()
1129 hwmgr->platform_descriptor.maxOverdriveVDDC = in init_overdrive_limits_V1_4()
1132 hwmgr->platform_descriptor.overdriveVDDCStep = 0; in init_overdrive_limits_V1_4()
1136 static int init_overdrive_limits_V2_1(struct pp_hwmgr *hwmgr, in init_overdrive_limits_V2_1() argument
1155 hwmgr->platform_descriptor.overdriveLimit.engineClock = le32_to_cpu(header->ulMaxEngineClock); in init_overdrive_limits_V2_1()
1156 hwmgr->platform_descriptor.overdriveLimit.memoryClock = le32_to_cpu(header->ulMaxMemoryClock); in init_overdrive_limits_V2_1()
1159 hwmgr->platform_descriptor.minOverdriveVDDC = 0; in init_overdrive_limits_V2_1()
1160 hwmgr->platform_descriptor.maxOverdriveVDDC = 0; in init_overdrive_limits_V2_1()
1161 hwmgr->platform_descriptor.overdriveVDDCStep = 0; in init_overdrive_limits_V2_1()
1166 static int init_overdrive_limits(struct pp_hwmgr *hwmgr, in init_overdrive_limits() argument
1175 hwmgr->platform_descriptor.overdriveLimit.engineClock = 0; in init_overdrive_limits()
1176 hwmgr->platform_descriptor.overdriveLimit.memoryClock = 0; in init_overdrive_limits()
1177 hwmgr->platform_descriptor.minOverdriveVDDC = 0; in init_overdrive_limits()
1178 hwmgr->platform_descriptor.maxOverdriveVDDC = 0; in init_overdrive_limits()
1179 hwmgr->platform_descriptor.overdriveVDDCStep = 0; in init_overdrive_limits()
1181 if (hwmgr->chip_id == CHIP_RAVEN) in init_overdrive_limits()
1185 fw_info = smu_atom_get_data_table(hwmgr->adev, in init_overdrive_limits()
1191 result = init_overdrive_limits_V1_4(hwmgr, in init_overdrive_limits()
1197 result = init_overdrive_limits_V2_1(hwmgr, in init_overdrive_limits()
1204 static int get_uvd_clock_voltage_limit_table(struct pp_hwmgr *hwmgr, in get_uvd_clock_voltage_limit_table() argument
1234 static int get_vce_clock_voltage_limit_table(struct pp_hwmgr *hwmgr, in get_vce_clock_voltage_limit_table() argument
1263 static int get_samu_clock_voltage_limit_table(struct pp_hwmgr *hwmgr, in get_samu_clock_voltage_limit_table() argument
1288 static int get_acp_clock_voltage_limit_table(struct pp_hwmgr *hwmgr, in get_acp_clock_voltage_limit_table() argument
1313 static int init_clock_voltage_dependency(struct pp_hwmgr *hwmgr, in init_clock_voltage_dependency() argument
1324 hwmgr->dyn_state.vddc_dependency_on_sclk = NULL; in init_clock_voltage_dependency()
1325 hwmgr->dyn_state.vddci_dependency_on_mclk = NULL; in init_clock_voltage_dependency()
1326 hwmgr->dyn_state.vddc_dependency_on_mclk = NULL; in init_clock_voltage_dependency()
1327 hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL; in init_clock_voltage_dependency()
1328 hwmgr->dyn_state.mvdd_dependency_on_mclk = NULL; in init_clock_voltage_dependency()
1329 hwmgr->dyn_state.vce_clock_voltage_dependency_table = NULL; in init_clock_voltage_dependency()
1330 hwmgr->dyn_state.uvd_clock_voltage_dependency_table = NULL; in init_clock_voltage_dependency()
1331 hwmgr->dyn_state.samu_clock_voltage_dependency_table = NULL; in init_clock_voltage_dependency()
1332 hwmgr->dyn_state.acp_clock_voltage_dependency_table = NULL; in init_clock_voltage_dependency()
1333 hwmgr->dyn_state.ppm_parameter_table = NULL; in init_clock_voltage_dependency()
1334 hwmgr->dyn_state.vdd_gfx_dependency_on_sclk = NULL; in init_clock_voltage_dependency()
1337 hwmgr, powerplay_table); in init_clock_voltage_dependency()
1338 table_offset = get_vce_clock_voltage_limit_table_offset(hwmgr, in init_clock_voltage_dependency()
1347 result = get_vce_clock_voltage_limit_table(hwmgr, in init_clock_voltage_dependency()
1348 &hwmgr->dyn_state.vce_clock_voltage_dependency_table, in init_clock_voltage_dependency()
1352 uvd_clock_info_array_offset = get_uvd_clock_info_array_offset(hwmgr, powerplay_table); in init_clock_voltage_dependency()
1353 table_offset = get_uvd_clock_voltage_limit_table_offset(hwmgr, powerplay_table); in init_clock_voltage_dependency()
1362 result = get_uvd_clock_voltage_limit_table(hwmgr, in init_clock_voltage_dependency()
1363 &hwmgr->dyn_state.uvd_clock_voltage_dependency_table, ptable, array); in init_clock_voltage_dependency()
1366 table_offset = get_samu_clock_voltage_limit_table_offset(hwmgr, in init_clock_voltage_dependency()
1373 result = get_samu_clock_voltage_limit_table(hwmgr, in init_clock_voltage_dependency()
1374 &hwmgr->dyn_state.samu_clock_voltage_dependency_table, ptable); in init_clock_voltage_dependency()
1377 table_offset = get_acp_clock_voltage_limit_table_offset(hwmgr, in init_clock_voltage_dependency()
1384 result = get_acp_clock_voltage_limit_table(hwmgr, in init_clock_voltage_dependency()
1385 &hwmgr->dyn_state.acp_clock_voltage_dependency_table, ptable); in init_clock_voltage_dependency()
1388 table_offset = get_cacp_tdp_table_offset(hwmgr, powerplay_table); in init_clock_voltage_dependency()
1396 result = get_cac_tdp_table(hwmgr, &hwmgr->dyn_state.cac_dtp_table, in init_clock_voltage_dependency()
1399 hwmgr->dyn_state.cac_dtp_table->usDefaultTargetOperatingTemp = in init_clock_voltage_dependency()
1405 result = get_cac_tdp_table(hwmgr, in init_clock_voltage_dependency()
1406 &hwmgr->dyn_state.cac_dtp_table, in init_clock_voltage_dependency()
1419 result = get_clock_voltage_dependency_table(hwmgr, in init_clock_voltage_dependency()
1420 &hwmgr->dyn_state.vddc_dependency_on_sclk, table); in init_clock_voltage_dependency()
1427 result = get_clock_voltage_dependency_table(hwmgr, in init_clock_voltage_dependency()
1428 &hwmgr->dyn_state.vddci_dependency_on_mclk, table); in init_clock_voltage_dependency()
1435 result = get_clock_voltage_dependency_table(hwmgr, in init_clock_voltage_dependency()
1436 &hwmgr->dyn_state.vddc_dependency_on_mclk, table); in init_clock_voltage_dependency()
1443 result = get_clock_voltage_limit(hwmgr, in init_clock_voltage_dependency()
1444 &hwmgr->dyn_state.max_clock_voltage_on_dc, limit_table); in init_clock_voltage_dependency()
1447 if (result == 0 && (NULL != hwmgr->dyn_state.vddc_dependency_on_mclk) && in init_clock_voltage_dependency()
1448 (0 != hwmgr->dyn_state.vddc_dependency_on_mclk->count)) in init_clock_voltage_dependency()
1449 result = get_valid_clk(hwmgr, &hwmgr->dyn_state.valid_mclk_values, in init_clock_voltage_dependency()
1450 hwmgr->dyn_state.vddc_dependency_on_mclk); in init_clock_voltage_dependency()
1452 if(result == 0 && (NULL != hwmgr->dyn_state.vddc_dependency_on_sclk) && in init_clock_voltage_dependency()
1453 (0 != hwmgr->dyn_state.vddc_dependency_on_sclk->count)) in init_clock_voltage_dependency()
1454 result = get_valid_clk(hwmgr, in init_clock_voltage_dependency()
1455 &hwmgr->dyn_state.valid_sclk_values, in init_clock_voltage_dependency()
1456 hwmgr->dyn_state.vddc_dependency_on_sclk); in init_clock_voltage_dependency()
1462 result = get_clock_voltage_dependency_table(hwmgr, in init_clock_voltage_dependency()
1463 &hwmgr->dyn_state.mvdd_dependency_on_mclk, table); in init_clock_voltage_dependency()
1467 table_offset = get_sclk_vdd_gfx_clock_voltage_dependency_table_offset(hwmgr, in init_clock_voltage_dependency()
1473 result = get_clock_voltage_dependency_table(hwmgr, in init_clock_voltage_dependency()
1474 &hwmgr->dyn_state.vdd_gfx_dependency_on_sclk, table); in init_clock_voltage_dependency()
1480 static int get_cac_leakage_table(struct pp_hwmgr *hwmgr, in get_cac_leakage_table() argument
1487 if (!hwmgr || !table || !ptable) in get_cac_leakage_table()
1498 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, in get_cac_leakage_table()
1514 static int get_platform_power_management_table(struct pp_hwmgr *hwmgr, in get_platform_power_management_table() argument
1532 hwmgr->dyn_state.ppm_parameter_table = ptr; in get_platform_power_management_table()
1537 static int init_dpm2_parameters(struct pp_hwmgr *hwmgr, in init_dpm2_parameters() argument
1556 hwmgr->platform_descriptor.TDPLimit = le32_to_cpu(ptable5->ulTDPLimit); in init_dpm2_parameters()
1557 hwmgr->platform_descriptor.nearTDPLimit = le32_to_cpu(ptable5->ulNearTDPLimit); in init_dpm2_parameters()
1559 hwmgr->platform_descriptor.TDPODLimit = le16_to_cpu(ptable5->usTDPODLimit); in init_dpm2_parameters()
1560 hwmgr->platform_descriptor.TDPAdjustment = 0; in init_dpm2_parameters()
1562 hwmgr->platform_descriptor.VidAdjustment = 0; in init_dpm2_parameters()
1563 hwmgr->platform_descriptor.VidAdjustmentPolarity = 0; in init_dpm2_parameters()
1564 hwmgr->platform_descriptor.VidMinLimit = 0; in init_dpm2_parameters()
1565 hwmgr->platform_descriptor.VidMaxLimit = 1500000; in init_dpm2_parameters()
1566 hwmgr->platform_descriptor.VidStep = 6250; in init_dpm2_parameters()
1568 hwmgr->platform_descriptor.nearTDPLimitAdjusted = le32_to_cpu(ptable5->ulNearTDPLimit); in init_dpm2_parameters()
1570 if (hwmgr->platform_descriptor.TDPODLimit != 0) in init_dpm2_parameters()
1571 phm_cap_set(hwmgr->platform_descriptor.platformCaps, in init_dpm2_parameters()
1574 hwmgr->platform_descriptor.SQRampingThreshold = le32_to_cpu(ptable5->ulSQRampingThreshold); in init_dpm2_parameters()
1576 hwmgr->platform_descriptor.CACLeakage = le32_to_cpu(ptable5->ulCACLeakage); in init_dpm2_parameters()
1578 hwmgr->dyn_state.cac_leakage_table = NULL; in init_dpm2_parameters()
1584 result = get_cac_leakage_table(hwmgr, in init_dpm2_parameters()
1585 &hwmgr->dyn_state.cac_leakage_table, pCAC_leakage_table); in init_dpm2_parameters()
1588 hwmgr->platform_descriptor.LoadLineSlope = le16_to_cpu(ptable5->usLoadLineSlope); in init_dpm2_parameters()
1590 hwmgr->dyn_state.ppm_parameter_table = NULL; in init_dpm2_parameters()
1602 if (0 == get_platform_power_management_table(hwmgr, atom_ppm_table)) in init_dpm2_parameters()
1603 phm_cap_set(hwmgr->platform_descriptor.platformCaps, in init_dpm2_parameters()
1611 static int init_phase_shedding_table(struct pp_hwmgr *hwmgr, in init_phase_shedding_table() argument
1642 hwmgr->dyn_state.vddc_phase_shed_limits_table = table; in init_phase_shedding_table()
1650 struct pp_hwmgr *hwmgr) in get_number_of_vce_state_table_entries() argument
1653 get_powerplay_table(hwmgr); in get_number_of_vce_state_table_entries()
1655 get_vce_state_table(hwmgr, table); in get_number_of_vce_state_table_entries()
1663 static int get_vce_state_table_entry(struct pp_hwmgr *hwmgr, in get_vce_state_table_entry() argument
1669 const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table = get_powerplay_table(hwmgr); in get_vce_state_table_entry()
1671 const ATOM_PPLIB_VCE_State_Table *vce_state_table = get_vce_state_table(hwmgr, powerplay_table); in get_vce_state_table_entry()
1673 …unsigned short vce_clock_info_array_offset = get_vce_clock_info_array_offset(hwmgr, powerplay_tabl… in get_vce_state_table_entry()
1697 static int pp_tables_initialize(struct pp_hwmgr *hwmgr) in pp_tables_initialize() argument
1702 if (hwmgr->chip_id == CHIP_RAVEN) in pp_tables_initialize()
1705 hwmgr->need_pp_table_upload = true; in pp_tables_initialize()
1707 powerplay_table = get_powerplay_table(hwmgr); in pp_tables_initialize()
1709 result = init_powerplay_tables(hwmgr, powerplay_table); in pp_tables_initialize()
1714 result = set_platform_caps(hwmgr, in pp_tables_initialize()
1720 result = init_thermal_controller(hwmgr, powerplay_table); in pp_tables_initialize()
1725 result = init_overdrive_limits(hwmgr, powerplay_table); in pp_tables_initialize()
1730 result = init_clock_voltage_dependency(hwmgr, in pp_tables_initialize()
1736 result = init_dpm2_parameters(hwmgr, powerplay_table); in pp_tables_initialize()
1741 result = init_phase_shedding_table(hwmgr, powerplay_table); in pp_tables_initialize()
1749 static int pp_tables_uninitialize(struct pp_hwmgr *hwmgr) in pp_tables_uninitialize() argument
1751 if (hwmgr->chip_id == CHIP_RAVEN) in pp_tables_uninitialize()
1754 kfree(hwmgr->dyn_state.vddc_dependency_on_sclk); in pp_tables_uninitialize()
1755 hwmgr->dyn_state.vddc_dependency_on_sclk = NULL; in pp_tables_uninitialize()
1757 kfree(hwmgr->dyn_state.vddci_dependency_on_mclk); in pp_tables_uninitialize()
1758 hwmgr->dyn_state.vddci_dependency_on_mclk = NULL; in pp_tables_uninitialize()
1760 kfree(hwmgr->dyn_state.vddc_dependency_on_mclk); in pp_tables_uninitialize()
1761 hwmgr->dyn_state.vddc_dependency_on_mclk = NULL; in pp_tables_uninitialize()
1763 kfree(hwmgr->dyn_state.mvdd_dependency_on_mclk); in pp_tables_uninitialize()
1764 hwmgr->dyn_state.mvdd_dependency_on_mclk = NULL; in pp_tables_uninitialize()
1766 kfree(hwmgr->dyn_state.valid_mclk_values); in pp_tables_uninitialize()
1767 hwmgr->dyn_state.valid_mclk_values = NULL; in pp_tables_uninitialize()
1769 kfree(hwmgr->dyn_state.valid_sclk_values); in pp_tables_uninitialize()
1770 hwmgr->dyn_state.valid_sclk_values = NULL; in pp_tables_uninitialize()
1772 kfree(hwmgr->dyn_state.cac_leakage_table); in pp_tables_uninitialize()
1773 hwmgr->dyn_state.cac_leakage_table = NULL; in pp_tables_uninitialize()
1775 kfree(hwmgr->dyn_state.vddc_phase_shed_limits_table); in pp_tables_uninitialize()
1776 hwmgr->dyn_state.vddc_phase_shed_limits_table = NULL; in pp_tables_uninitialize()
1778 kfree(hwmgr->dyn_state.vce_clock_voltage_dependency_table); in pp_tables_uninitialize()
1779 hwmgr->dyn_state.vce_clock_voltage_dependency_table = NULL; in pp_tables_uninitialize()
1781 kfree(hwmgr->dyn_state.uvd_clock_voltage_dependency_table); in pp_tables_uninitialize()
1782 hwmgr->dyn_state.uvd_clock_voltage_dependency_table = NULL; in pp_tables_uninitialize()
1784 kfree(hwmgr->dyn_state.samu_clock_voltage_dependency_table); in pp_tables_uninitialize()
1785 hwmgr->dyn_state.samu_clock_voltage_dependency_table = NULL; in pp_tables_uninitialize()
1787 kfree(hwmgr->dyn_state.acp_clock_voltage_dependency_table); in pp_tables_uninitialize()
1788 hwmgr->dyn_state.acp_clock_voltage_dependency_table = NULL; in pp_tables_uninitialize()
1790 kfree(hwmgr->dyn_state.cac_dtp_table); in pp_tables_uninitialize()
1791 hwmgr->dyn_state.cac_dtp_table = NULL; in pp_tables_uninitialize()
1793 kfree(hwmgr->dyn_state.ppm_parameter_table); in pp_tables_uninitialize()
1794 hwmgr->dyn_state.ppm_parameter_table = NULL; in pp_tables_uninitialize()
1796 kfree(hwmgr->dyn_state.vdd_gfx_dependency_on_sclk); in pp_tables_uninitialize()
1797 hwmgr->dyn_state.vdd_gfx_dependency_on_sclk = NULL; in pp_tables_uninitialize()