Lines Matching refs:hwmgr
202 int (*smu_init)(struct pp_hwmgr *hwmgr);
203 int (*smu_fini)(struct pp_hwmgr *hwmgr);
204 int (*start_smu)(struct pp_hwmgr *hwmgr);
205 int (*check_fw_load_finish)(struct pp_hwmgr *hwmgr,
207 int (*request_smu_load_fw)(struct pp_hwmgr *hwmgr);
208 int (*request_smu_load_specific_fw)(struct pp_hwmgr *hwmgr,
210 uint32_t (*get_argument)(struct pp_hwmgr *hwmgr);
211 int (*send_msg_to_smc)(struct pp_hwmgr *hwmgr, uint16_t msg);
212 int (*send_msg_to_smc_with_parameter)(struct pp_hwmgr *hwmgr,
214 int (*download_pptable_settings)(struct pp_hwmgr *hwmgr,
216 int (*upload_pptable_settings)(struct pp_hwmgr *hwmgr);
217 int (*update_smc_table)(struct pp_hwmgr *hwmgr, uint32_t type);
218 int (*process_firmware_header)(struct pp_hwmgr *hwmgr);
219 int (*update_sclk_threshold)(struct pp_hwmgr *hwmgr);
220 int (*thermal_setup_fan_table)(struct pp_hwmgr *hwmgr);
221 int (*thermal_avfs_enable)(struct pp_hwmgr *hwmgr);
222 int (*init_smc_table)(struct pp_hwmgr *hwmgr);
223 int (*populate_all_graphic_levels)(struct pp_hwmgr *hwmgr);
224 int (*populate_all_memory_levels)(struct pp_hwmgr *hwmgr);
225 int (*initialize_mc_reg_table)(struct pp_hwmgr *hwmgr);
228 bool (*is_dpm_running)(struct pp_hwmgr *hwmgr);
229 bool (*is_hw_avfs_present)(struct pp_hwmgr *hwmgr);
230 int (*update_dpm_settings)(struct pp_hwmgr *hwmgr, void *profile_setting);
231 …int (*smc_table_manager)(struct pp_hwmgr *hwmgr, uint8_t *table, uint16_t table_id, bool rw); /*rw…
232 int (*stop_smc)(struct pp_hwmgr *hwmgr);
241 int (*apply_state_adjust_rules)(struct pp_hwmgr *hwmgr,
245 int (*apply_clocks_adjust_rules)(struct pp_hwmgr *hwmgr);
255 int (*patch_boot_state)(struct pp_hwmgr *hwmgr,
258 int (*get_pp_table_entry)(struct pp_hwmgr *hwmgr,
260 int (*get_num_of_pp_table_entries)(struct pp_hwmgr *hwmgr);
261 int (*powerdown_uvd)(struct pp_hwmgr *hwmgr);
262 void (*powergate_vce)(struct pp_hwmgr *hwmgr, bool bgate);
263 void (*powergate_uvd)(struct pp_hwmgr *hwmgr, bool bgate);
264 void (*powergate_acp)(struct pp_hwmgr *hwmgr, bool bgate);
265 uint32_t (*get_mclk)(struct pp_hwmgr *hwmgr, bool low);
266 uint32_t (*get_sclk)(struct pp_hwmgr *hwmgr, bool low);
267 int (*power_state_set)(struct pp_hwmgr *hwmgr,
269 int (*notify_smc_display_config_after_ps_adjustment)(struct pp_hwmgr *hwmgr);
270 int (*pre_display_config_changed)(struct pp_hwmgr *hwmgr);
271 int (*display_config_changed)(struct pp_hwmgr *hwmgr);
272 int (*disable_clock_power_gating)(struct pp_hwmgr *hwmgr);
273 int (*update_clock_gatings)(struct pp_hwmgr *hwmgr,
275 int (*set_max_fan_rpm_output)(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm);
276 int (*set_max_fan_pwm_output)(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm);
277 int (*stop_thermal_controller)(struct pp_hwmgr *hwmgr);
278 int (*get_fan_speed_info)(struct pp_hwmgr *hwmgr, struct phm_fan_speed_info *fan_speed_info);
279 void (*set_fan_control_mode)(struct pp_hwmgr *hwmgr, uint32_t mode);
280 uint32_t (*get_fan_control_mode)(struct pp_hwmgr *hwmgr);
281 int (*set_fan_speed_pwm)(struct pp_hwmgr *hwmgr, uint32_t speed);
282 int (*get_fan_speed_pwm)(struct pp_hwmgr *hwmgr, uint32_t *speed);
283 int (*set_fan_speed_rpm)(struct pp_hwmgr *hwmgr, uint32_t speed);
284 int (*get_fan_speed_rpm)(struct pp_hwmgr *hwmgr, uint32_t *speed);
285 int (*reset_fan_speed_to_default)(struct pp_hwmgr *hwmgr);
286 int (*uninitialize_thermal_controller)(struct pp_hwmgr *hwmgr);
287 int (*register_irq_handlers)(struct pp_hwmgr *hwmgr);
288 bool (*check_smc_update_required_for_display_configuration)(struct pp_hwmgr *hwmgr);
289 int (*check_states_equal)(struct pp_hwmgr *hwmgr,
293 int (*set_cpu_power_state)(struct pp_hwmgr *hwmgr);
294 int (*store_cc6_data)(struct pp_hwmgr *hwmgr, uint32_t separation_time,
297 int (*get_dal_power_level)(struct pp_hwmgr *hwmgr,
301 int (*get_current_shallow_sleep_clocks)(struct pp_hwmgr *hwmgr,
303 …int (*get_clock_by_type)(struct pp_hwmgr *hwmgr, enum amd_pp_clock_type type, struct amd_pp_clocks…
304 int (*get_clock_by_type_with_latency)(struct pp_hwmgr *hwmgr,
307 int (*get_clock_by_type_with_voltage)(struct pp_hwmgr *hwmgr,
310 int (*set_watermarks_for_clocks_ranges)(struct pp_hwmgr *hwmgr, void *clock_ranges);
311 int (*display_clock_voltage_request)(struct pp_hwmgr *hwmgr,
313 int (*get_max_high_clocks)(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks);
314 int (*power_off_asic)(struct pp_hwmgr *hwmgr);
315 int (*force_clock_level)(struct pp_hwmgr *hwmgr, enum pp_clock_type type, uint32_t mask);
316 int (*emit_clock_levels)(struct pp_hwmgr *hwmgr,
318 int (*print_clock_levels)(struct pp_hwmgr *hwmgr, enum pp_clock_type type, char *buf);
319 int (*powergate_gfx)(struct pp_hwmgr *hwmgr, bool enable);
320 int (*get_sclk_od)(struct pp_hwmgr *hwmgr);
321 int (*set_sclk_od)(struct pp_hwmgr *hwmgr, uint32_t value);
322 int (*get_mclk_od)(struct pp_hwmgr *hwmgr);
323 int (*set_mclk_od)(struct pp_hwmgr *hwmgr, uint32_t value);
324 int (*read_sensor)(struct pp_hwmgr *hwmgr, int idx, void *value, int *size);
325 int (*avfs_control)(struct pp_hwmgr *hwmgr, bool enable);
326 int (*disable_smc_firmware_ctf)(struct pp_hwmgr *hwmgr);
327 int (*set_active_display_count)(struct pp_hwmgr *hwmgr, uint32_t count);
328 int (*set_min_deep_sleep_dcefclk)(struct pp_hwmgr *hwmgr, uint32_t clock);
329 int (*start_thermal_controller)(struct pp_hwmgr *hwmgr, struct PP_TemperatureRange *range);
330 int (*notify_cac_buffer_info)(struct pp_hwmgr *hwmgr,
336 int (*get_thermal_temperature_range)(struct pp_hwmgr *hwmgr,
338 int (*get_power_profile_mode)(struct pp_hwmgr *hwmgr, char *buf);
339 int (*set_power_profile_mode)(struct pp_hwmgr *hwmgr, long *input, uint32_t size);
340 int (*odn_edit_dpm_table)(struct pp_hwmgr *hwmgr,
343 int (*set_fine_grain_clk_vol)(struct pp_hwmgr *hwmgr,
346 int (*set_power_limit)(struct pp_hwmgr *hwmgr, uint32_t n);
347 int (*powergate_mmhub)(struct pp_hwmgr *hwmgr);
348 int (*smus_notify_pwe)(struct pp_hwmgr *hwmgr);
349 int (*powergate_sdma)(struct pp_hwmgr *hwmgr, bool bgate);
350 int (*enable_mgpu_fan_boost)(struct pp_hwmgr *hwmgr);
351 int (*set_hard_min_dcefclk_by_freq)(struct pp_hwmgr *hwmgr, uint32_t clock);
352 int (*set_hard_min_fclk_by_freq)(struct pp_hwmgr *hwmgr, uint32_t clock);
353 int (*set_hard_min_gfxclk_by_freq)(struct pp_hwmgr *hwmgr, uint32_t clock);
354 int (*set_soft_max_gfxclk_by_freq)(struct pp_hwmgr *hwmgr, uint32_t clock);
355 int (*get_asic_baco_capability)(struct pp_hwmgr *hwmgr, bool *cap);
356 int (*get_asic_baco_state)(struct pp_hwmgr *hwmgr, enum BACO_STATE *state);
357 int (*set_asic_baco_state)(struct pp_hwmgr *hwmgr, enum BACO_STATE state);
358 int (*get_ppfeature_status)(struct pp_hwmgr *hwmgr, char *buf);
359 int (*set_ppfeature_status)(struct pp_hwmgr *hwmgr, uint64_t ppfeature_masks);
360 int (*set_mp1_state)(struct pp_hwmgr *hwmgr, enum pp_mp1_state mp1_state);
361 int (*asic_reset)(struct pp_hwmgr *hwmgr, enum SMU_ASIC_RESET_MODE mode);
362 int (*smu_i2c_bus_access)(struct pp_hwmgr *hwmgr, bool aquire);
363 int (*set_df_cstate)(struct pp_hwmgr *hwmgr, enum pp_df_cstate state);
364 int (*set_xgmi_pstate)(struct pp_hwmgr *hwmgr, uint32_t pstate);
365 int (*disable_power_features_for_compute_performance)(struct pp_hwmgr *hwmgr,
367 ssize_t (*get_gpu_metrics)(struct pp_hwmgr *hwmgr, void **table);
368 int (*gfx_state_change)(struct pp_hwmgr *hwmgr, uint32_t state);
376 struct pp_hwmgr *hwmgr,
816 int hwmgr_early_init(struct pp_hwmgr *hwmgr);
817 int hwmgr_sw_init(struct pp_hwmgr *hwmgr);
818 int hwmgr_sw_fini(struct pp_hwmgr *hwmgr);
819 int hwmgr_hw_init(struct pp_hwmgr *hwmgr);
820 int hwmgr_hw_fini(struct pp_hwmgr *hwmgr);
821 int hwmgr_suspend(struct pp_hwmgr *hwmgr);
822 int hwmgr_resume(struct pp_hwmgr *hwmgr);
824 int hwmgr_handle_task(struct pp_hwmgr *hwmgr,
831 int smu7_init_function_pointers(struct pp_hwmgr *hwmgr);
832 int smu8_init_function_pointers(struct pp_hwmgr *hwmgr);
833 int vega12_hwmgr_init(struct pp_hwmgr *hwmgr);
834 int vega20_hwmgr_init(struct pp_hwmgr *hwmgr);