Lines Matching refs:lane_count
428 u8 lane_count; member
803 switch (it6505->lane_count) { in it6505_lane_termination_on()
815 switch (it6505->lane_count) { in it6505_lane_termination_on()
847 GENMASK(7, 8 - it6505->lane_count) : in it6505_lane_power_on()
848 GENMASK(3 + it6505->lane_count, 4)) | in it6505_lane_power_on()
1165 it6505->lane_count = MAX_LANE_COUNT; in it6505_variable_config()
1465 it6505->lane_count = link->num_lanes; in it6505_parse_link_capabilities()
1467 it6505->lane_count); in it6505_parse_link_capabilities()
1468 it6505->lane_count = min_t(int, it6505->lane_count, in it6505_parse_link_capabilities()
1543 (it6505->lane_count - 1) << 1); in it6505_lane_count_setup()
1560 it6505->lane_count, in it6505_link_training_setup()
1601 values[1] = it6505->lane_count; in it6505_drm_dp_link_configure()
1624 u8 lane_count) in it6505_check_max_voltage_swing_reached() argument
1628 for (i = 0; i < lane_count; i++) { in it6505_check_max_voltage_swing_reached()
1646 for (i = 0; i < it6505->lane_count; i++) { in step_train_lane_voltage_para_set()
1694 if (drm_dp_clock_recovery_ok(link_status, it6505->lane_count)) { in it6505_step_cr_train()
1702 it6505->lane_count)) in it6505_step_cr_train()
1705 for (j = 0; j < it6505->lane_count; j++) { in it6505_step_cr_train()
1766 if (!drm_dp_clock_recovery_ok(link_status, it6505->lane_count)) in it6505_step_eq_train()
1769 if (drm_dp_channel_eq_ok(link_status, it6505->lane_count)) { in it6505_step_eq_train()
1778 for (i = 0; i < it6505->lane_count; i++) { in it6505_step_eq_train()
2091 if (ret < 0 || !drm_dp_channel_eq_ok(link_status, it6505->lane_count) || in it6505_hdcp_work()
2312 if (!drm_dp_channel_eq_ok(link_status, it6505->lane_count)) { in it6505_process_hpd_irq()