Lines Matching refs:tc
331 static inline int tc_poll_timeout(struct tc_data *tc, unsigned int addr, in tc_poll_timeout() argument
338 return regmap_read_poll_timeout(tc->regmap, addr, val, in tc_poll_timeout()
343 static int tc_aux_wait_busy(struct tc_data *tc) in tc_aux_wait_busy() argument
345 return tc_poll_timeout(tc, DP0_AUXSTATUS, AUX_BUSY, 0, 100, 100000); in tc_aux_wait_busy()
348 static int tc_aux_write_data(struct tc_data *tc, const void *data, in tc_aux_write_data() argument
356 ret = regmap_raw_write(tc->regmap, DP0_AUXWDATA(0), auxwdata, count); in tc_aux_write_data()
363 static int tc_aux_read_data(struct tc_data *tc, void *data, size_t size) in tc_aux_read_data() argument
368 ret = regmap_raw_read(tc->regmap, DP0_AUXRDATA(0), auxrdata, count); in tc_aux_read_data()
392 struct tc_data *tc = aux_to_tc(aux); in tc_aux_transfer() local
398 ret = tc_aux_wait_busy(tc); in tc_aux_transfer()
409 ret = tc_aux_write_data(tc, msg->buffer, size); in tc_aux_transfer()
419 ret = regmap_write(tc->regmap, DP0_AUXADDR, msg->address); in tc_aux_transfer()
423 ret = regmap_write(tc->regmap, DP0_AUXCFG0, tc_auxcfg0(msg, size)); in tc_aux_transfer()
427 ret = tc_aux_wait_busy(tc); in tc_aux_transfer()
431 ret = regmap_read(tc->regmap, DP0_AUXSTATUS, &auxstatus); in tc_aux_transfer()
451 return tc_aux_read_data(tc, msg->buffer, size); in tc_aux_transfer()
476 static u32 tc_srcctrl(struct tc_data *tc) in tc_srcctrl() argument
484 if (tc->link.scrambler_dis) in tc_srcctrl()
486 if (tc->link.spread) in tc_srcctrl()
488 if (tc->link.num_lanes == 2) in tc_srcctrl()
490 if (tc->link.rate != 162000) in tc_srcctrl()
495 static int tc_pllupdate(struct tc_data *tc, unsigned int pllctrl) in tc_pllupdate() argument
499 ret = regmap_write(tc->regmap, pllctrl, PLLUPDATE | PLLEN); in tc_pllupdate()
509 static int tc_pxl_pll_en(struct tc_data *tc, u32 refclk, u32 pixelclock) in tc_pxl_pll_en() argument
528 if (tc->bridge.type == DRM_MODE_CONNECTOR_DPI) { in tc_pxl_pll_en()
536 dev_dbg(tc->dev, "PLL: requested %d pixelclock, ref %d\n", pixelclock, in tc_pxl_pll_en()
580 dev_err(tc->dev, "Failed to calc clock for %d pixelclock\n", in tc_pxl_pll_en()
585 dev_dbg(tc->dev, "PLL: got %d, delta %d\n", best_pixelclock, in tc_pxl_pll_en()
587 dev_dbg(tc->dev, "PLL: %d / %d / %d * %d / %d\n", refclk, in tc_pxl_pll_en()
600 ret = regmap_write(tc->regmap, PXL_PLLCTRL, PLLBYP | PLLEN); in tc_pxl_pll_en()
611 ret = regmap_write(tc->regmap, PXL_PLLPARAM, pxl_pllparam); in tc_pxl_pll_en()
616 return tc_pllupdate(tc, PXL_PLLCTRL); in tc_pxl_pll_en()
619 static int tc_pxl_pll_dis(struct tc_data *tc) in tc_pxl_pll_dis() argument
622 return regmap_write(tc->regmap, PXL_PLLCTRL, PLLBYP); in tc_pxl_pll_dis()
625 static int tc_stream_clock_calc(struct tc_data *tc) in tc_stream_clock_calc() argument
642 return regmap_write(tc->regmap, DP0_VIDMNGEN1, 32768); in tc_stream_clock_calc()
645 static int tc_set_syspllparam(struct tc_data *tc) in tc_set_syspllparam() argument
650 rate = clk_get_rate(tc->refclk); in tc_set_syspllparam()
665 dev_err(tc->dev, "Invalid refclk rate: %lu Hz\n", rate); in tc_set_syspllparam()
669 return regmap_write(tc->regmap, SYS_PLLPARAM, pllparam); in tc_set_syspllparam()
672 static int tc_aux_link_setup(struct tc_data *tc) in tc_aux_link_setup() argument
678 ret = tc_set_syspllparam(tc); in tc_aux_link_setup()
682 ret = regmap_write(tc->regmap, DP_PHY_CTRL, in tc_aux_link_setup()
690 ret = tc_pllupdate(tc, DP0_PLLCTRL); in tc_aux_link_setup()
694 ret = tc_pllupdate(tc, DP1_PLLCTRL); in tc_aux_link_setup()
698 ret = tc_poll_timeout(tc, DP_PHY_CTRL, PHY_RDY, PHY_RDY, 100, 100000); in tc_aux_link_setup()
700 dev_err(tc->dev, "Timeout waiting for PHY to become ready"); in tc_aux_link_setup()
711 ret = regmap_write(tc->regmap, DP0_AUXCFG1, dp0_auxcfg1); in tc_aux_link_setup()
716 tc->aux.name = "TC358767 AUX i2c adapter"; in tc_aux_link_setup()
717 tc->aux.dev = tc->dev; in tc_aux_link_setup()
718 tc->aux.transfer = tc_aux_transfer; in tc_aux_link_setup()
719 drm_dp_aux_init(&tc->aux); in tc_aux_link_setup()
723 dev_err(tc->dev, "tc_aux_link_setup failed: %d\n", ret); in tc_aux_link_setup()
727 static int tc_get_display_props(struct tc_data *tc) in tc_get_display_props() argument
735 ret = drm_dp_dpcd_read(&tc->aux, DP_DPCD_REV, tc->link.dpcd, in tc_get_display_props()
740 revision = tc->link.dpcd[DP_DPCD_REV]; in tc_get_display_props()
741 rate = drm_dp_max_link_rate(tc->link.dpcd); in tc_get_display_props()
742 num_lanes = drm_dp_max_lane_count(tc->link.dpcd); in tc_get_display_props()
745 dev_dbg(tc->dev, "Falling to 2.7 Gbps rate\n"); in tc_get_display_props()
749 tc->link.rate = rate; in tc_get_display_props()
752 dev_dbg(tc->dev, "Falling to 2 lanes\n"); in tc_get_display_props()
756 tc->link.num_lanes = num_lanes; in tc_get_display_props()
758 ret = drm_dp_dpcd_readb(&tc->aux, DP_MAX_DOWNSPREAD, ®); in tc_get_display_props()
761 tc->link.spread = reg & DP_MAX_DOWNSPREAD_0_5; in tc_get_display_props()
763 ret = drm_dp_dpcd_readb(&tc->aux, DP_MAIN_LINK_CHANNEL_CODING, ®); in tc_get_display_props()
767 tc->link.scrambler_dis = false; in tc_get_display_props()
769 ret = drm_dp_dpcd_readb(&tc->aux, DP_EDP_CONFIGURATION_SET, ®); in tc_get_display_props()
772 tc->link.assr = reg & DP_ALTERNATE_SCRAMBLER_RESET_ENABLE; in tc_get_display_props()
774 dev_dbg(tc->dev, "DPCD rev: %d.%d, rate: %s, lanes: %d, framing: %s\n", in tc_get_display_props()
776 (tc->link.rate == 162000) ? "1.62Gbps" : "2.7Gbps", in tc_get_display_props()
777 tc->link.num_lanes, in tc_get_display_props()
778 drm_dp_enhanced_frame_cap(tc->link.dpcd) ? in tc_get_display_props()
780 dev_dbg(tc->dev, "Downspread: %s, scrambler: %s\n", in tc_get_display_props()
781 tc->link.spread ? "0.5%" : "0.0%", in tc_get_display_props()
782 tc->link.scrambler_dis ? "disabled" : "enabled"); in tc_get_display_props()
783 dev_dbg(tc->dev, "Display ASSR: %d, TC358767 ASSR: %d\n", in tc_get_display_props()
784 tc->link.assr, tc->assr); in tc_get_display_props()
789 dev_err(tc->dev, "failed to read DPCD: %d\n", ret); in tc_get_display_props()
793 static int tc_set_common_video_mode(struct tc_data *tc, in tc_set_common_video_mode() argument
804 dev_dbg(tc->dev, "set mode %dx%d\n", in tc_set_common_video_mode()
806 dev_dbg(tc->dev, "H margin %d,%d sync %d\n", in tc_set_common_video_mode()
808 dev_dbg(tc->dev, "V margin %d,%d sync %d\n", in tc_set_common_video_mode()
810 dev_dbg(tc->dev, "total: %dx%d\n", mode->htotal, mode->vtotal); in tc_set_common_video_mode()
819 ret = regmap_write(tc->regmap, VPCTRL0, in tc_set_common_video_mode()
825 ret = regmap_write(tc->regmap, HTIM01, in tc_set_common_video_mode()
831 ret = regmap_write(tc->regmap, HTIM02, in tc_set_common_video_mode()
837 ret = regmap_write(tc->regmap, VTIM01, in tc_set_common_video_mode()
843 ret = regmap_write(tc->regmap, VTIM02, in tc_set_common_video_mode()
849 ret = regmap_write(tc->regmap, VFUEN0, VFUEN); /* update settings */ in tc_set_common_video_mode()
854 ret = regmap_write(tc->regmap, TSTCTL, in tc_set_common_video_mode()
864 static int tc_set_dpi_video_mode(struct tc_data *tc, in tc_set_dpi_video_mode() argument
869 if (tc->mode.flags & DRM_MODE_FLAG_NHSYNC) in tc_set_dpi_video_mode()
872 if (tc->mode.flags & DRM_MODE_FLAG_NVSYNC) in tc_set_dpi_video_mode()
875 return regmap_write(tc->regmap, POCTRL, value); in tc_set_dpi_video_mode()
878 static int tc_set_edp_video_mode(struct tc_data *tc, in tc_set_edp_video_mode() argument
902 out_bw = tc->link.num_lanes * tc->link.rate; in tc_set_edp_video_mode()
907 ret = regmap_write(tc->regmap, DP0_VIDSYNCDELAY, in tc_set_edp_video_mode()
911 ret = regmap_write(tc->regmap, DP0_TOTALVAL, in tc_set_edp_video_mode()
917 ret = regmap_write(tc->regmap, DP0_STARTVAL, in tc_set_edp_video_mode()
923 ret = regmap_write(tc->regmap, DP0_ACTIVEVAL, in tc_set_edp_video_mode()
938 ret = regmap_write(tc->regmap, DP0_SYNCVAL, dp0_syncval); in tc_set_edp_video_mode()
950 ret = regmap_write(tc->regmap, DPIPXLFMT, dpipxlfmt); in tc_set_edp_video_mode()
954 ret = regmap_write(tc->regmap, DP0_MISC, in tc_set_edp_video_mode()
961 static int tc_wait_link_training(struct tc_data *tc) in tc_wait_link_training() argument
966 ret = tc_poll_timeout(tc, DP0_LTSTAT, LT_LOOPDONE, in tc_wait_link_training()
969 dev_err(tc->dev, "Link training timeout waiting for LT_LOOPDONE!\n"); in tc_wait_link_training()
973 ret = regmap_read(tc->regmap, DP0_LTSTAT, &value); in tc_wait_link_training()
980 static int tc_main_link_enable(struct tc_data *tc) in tc_main_link_enable() argument
982 struct drm_dp_aux *aux = &tc->aux; in tc_main_link_enable()
983 struct device *dev = tc->dev; in tc_main_link_enable()
989 dev_dbg(tc->dev, "link enable\n"); in tc_main_link_enable()
991 ret = regmap_read(tc->regmap, DP0CTL, &value); in tc_main_link_enable()
996 ret = regmap_write(tc->regmap, DP0CTL, 0); in tc_main_link_enable()
1001 ret = regmap_write(tc->regmap, DP0_SRCCTRL, tc_srcctrl(tc)); in tc_main_link_enable()
1005 ret = regmap_write(tc->regmap, DP1_SRCCTRL, in tc_main_link_enable()
1006 (tc->link.spread ? DP0_SRCCTRL_SSCG : 0) | in tc_main_link_enable()
1007 ((tc->link.rate != 162000) ? DP0_SRCCTRL_BW27 : 0)); in tc_main_link_enable()
1011 ret = tc_set_syspllparam(tc); in tc_main_link_enable()
1017 if (tc->link.num_lanes == 2) in tc_main_link_enable()
1020 ret = regmap_write(tc->regmap, DP_PHY_CTRL, dp_phy_ctrl); in tc_main_link_enable()
1025 ret = tc_pllupdate(tc, DP0_PLLCTRL); in tc_main_link_enable()
1029 ret = tc_pllupdate(tc, DP1_PLLCTRL); in tc_main_link_enable()
1035 ret = regmap_write(tc->regmap, DP_PHY_CTRL, dp_phy_ctrl); in tc_main_link_enable()
1038 ret = regmap_write(tc->regmap, DP_PHY_CTRL, dp_phy_ctrl); in tc_main_link_enable()
1040 ret = tc_poll_timeout(tc, DP_PHY_CTRL, PHY_RDY, PHY_RDY, 500, 100000); in tc_main_link_enable()
1047 ret = regmap_update_bits(tc->regmap, DP0_MISC, BPC_8, BPC_8); in tc_main_link_enable()
1058 if (tc->assr != tc->link.assr) { in tc_main_link_enable()
1060 tc->assr); in tc_main_link_enable()
1062 tmp[0] = tc->assr; in tc_main_link_enable()
1071 if (tmp[0] != tc->assr) { in tc_main_link_enable()
1073 tc->assr); in tc_main_link_enable()
1075 tc->link.scrambler_dis = true; in tc_main_link_enable()
1080 tmp[0] = drm_dp_link_rate_to_bw_code(tc->link.rate); in tc_main_link_enable()
1081 tmp[1] = tc->link.num_lanes; in tc_main_link_enable()
1083 if (drm_dp_enhanced_frame_cap(tc->link.dpcd)) in tc_main_link_enable()
1091 tmp[0] = tc->link.spread ? DP_SPREAD_AMP_0_5 : 0x00; in tc_main_link_enable()
1108 ret = regmap_write(tc->regmap, DP0_SNKLTCTRL, in tc_main_link_enable()
1114 ret = regmap_write(tc->regmap, DP0_LTLOOPCTRL, in tc_main_link_enable()
1121 ret = regmap_write(tc->regmap, DP0_SRCCTRL, in tc_main_link_enable()
1122 tc_srcctrl(tc) | DP0_SRCCTRL_SCRMBLDIS | in tc_main_link_enable()
1129 ret = regmap_write(tc->regmap, DP0CTL, in tc_main_link_enable()
1130 (drm_dp_enhanced_frame_cap(tc->link.dpcd) ? in tc_main_link_enable()
1137 ret = tc_wait_link_training(tc); in tc_main_link_enable()
1142 dev_err(tc->dev, "Link training phase 1 failed: %s\n", in tc_main_link_enable()
1150 ret = regmap_write(tc->regmap, DP0_SNKLTCTRL, in tc_main_link_enable()
1156 ret = regmap_write(tc->regmap, DP0_SRCCTRL, in tc_main_link_enable()
1157 tc_srcctrl(tc) | DP0_SRCCTRL_SCRMBLDIS | in tc_main_link_enable()
1164 ret = tc_wait_link_training(tc); in tc_main_link_enable()
1169 dev_err(tc->dev, "Link training phase 2 failed: %s\n", in tc_main_link_enable()
1184 ret = regmap_write(tc->regmap, DP0_SRCCTRL, tc_srcctrl(tc) | in tc_main_link_enable()
1191 tmp[0] = tc->link.scrambler_dis ? DP_LINK_SCRAMBLING_DISABLE : 0x00; in tc_main_link_enable()
1206 dev_err(tc->dev, "Lane 0 failed: %x\n", value); in tc_main_link_enable()
1210 if (tc->link.num_lanes == 2) { in tc_main_link_enable()
1214 dev_err(tc->dev, "Lane 1 failed: %x\n", value); in tc_main_link_enable()
1219 dev_err(tc->dev, "Interlane align failed\n"); in tc_main_link_enable()
1236 dev_err(tc->dev, "Failed to read DPCD: %d\n", ret); in tc_main_link_enable()
1239 dev_err(tc->dev, "Failed to write DPCD: %d\n", ret); in tc_main_link_enable()
1243 static int tc_main_link_disable(struct tc_data *tc) in tc_main_link_disable() argument
1247 dev_dbg(tc->dev, "link disable\n"); in tc_main_link_disable()
1249 ret = regmap_write(tc->regmap, DP0_SRCCTRL, 0); in tc_main_link_disable()
1253 ret = regmap_write(tc->regmap, DP0CTL, 0); in tc_main_link_disable()
1257 return regmap_update_bits(tc->regmap, DP_PHY_CTRL, in tc_main_link_disable()
1262 static int tc_dsi_rx_enable(struct tc_data *tc) in tc_dsi_rx_enable() argument
1267 regmap_write(tc->regmap, PPI_D0S_CLRSIPOCOUNT, 25); in tc_dsi_rx_enable()
1268 regmap_write(tc->regmap, PPI_D1S_CLRSIPOCOUNT, 25); in tc_dsi_rx_enable()
1269 regmap_write(tc->regmap, PPI_D2S_CLRSIPOCOUNT, 25); in tc_dsi_rx_enable()
1270 regmap_write(tc->regmap, PPI_D3S_CLRSIPOCOUNT, 25); in tc_dsi_rx_enable()
1271 regmap_write(tc->regmap, PPI_D0S_ATMR, 0); in tc_dsi_rx_enable()
1272 regmap_write(tc->regmap, PPI_D1S_ATMR, 0); in tc_dsi_rx_enable()
1273 regmap_write(tc->regmap, PPI_TX_RX_TA, TTA_GET | TTA_SURE); in tc_dsi_rx_enable()
1274 regmap_write(tc->regmap, PPI_LPTXTIMECNT, LPX_PERIOD); in tc_dsi_rx_enable()
1276 value = ((LANEENABLE_L0EN << tc->dsi->lanes) - LANEENABLE_L0EN) | in tc_dsi_rx_enable()
1278 regmap_write(tc->regmap, PPI_LANEENABLE, value); in tc_dsi_rx_enable()
1279 regmap_write(tc->regmap, DSI_LANEENABLE, value); in tc_dsi_rx_enable()
1287 ret = regmap_write(tc->regmap, SYSCTRL, value); in tc_dsi_rx_enable()
1293 regmap_write(tc->regmap, PPI_STARTPPI, PPI_START_FUNCTION); in tc_dsi_rx_enable()
1294 regmap_write(tc->regmap, DSI_STARTDSI, DSI_RX_START); in tc_dsi_rx_enable()
1299 static int tc_dpi_rx_enable(struct tc_data *tc) in tc_dpi_rx_enable() argument
1309 return regmap_write(tc->regmap, SYSCTRL, value); in tc_dpi_rx_enable()
1312 static int tc_dpi_stream_enable(struct tc_data *tc) in tc_dpi_stream_enable() argument
1316 dev_dbg(tc->dev, "enable video stream\n"); in tc_dpi_stream_enable()
1319 ret = tc_set_syspllparam(tc); in tc_dpi_stream_enable()
1327 ret = tc_pllupdate(tc, DP0_PLLCTRL); in tc_dpi_stream_enable()
1331 ret = tc_pllupdate(tc, DP1_PLLCTRL); in tc_dpi_stream_enable()
1336 ret = tc_pxl_pll_en(tc, clk_get_rate(tc->refclk), in tc_dpi_stream_enable()
1337 1000 * tc->mode.clock); in tc_dpi_stream_enable()
1341 ret = tc_set_common_video_mode(tc, &tc->mode); in tc_dpi_stream_enable()
1345 ret = tc_set_dpi_video_mode(tc, &tc->mode); in tc_dpi_stream_enable()
1349 return tc_dsi_rx_enable(tc); in tc_dpi_stream_enable()
1352 static int tc_dpi_stream_disable(struct tc_data *tc) in tc_dpi_stream_disable() argument
1354 dev_dbg(tc->dev, "disable video stream\n"); in tc_dpi_stream_disable()
1356 tc_pxl_pll_dis(tc); in tc_dpi_stream_disable()
1361 static int tc_edp_stream_enable(struct tc_data *tc) in tc_edp_stream_enable() argument
1366 dev_dbg(tc->dev, "enable video stream\n"); in tc_edp_stream_enable()
1379 if (tc->input_connector_dsi || tc_test_pattern) { in tc_edp_stream_enable()
1380 ret = tc_pxl_pll_en(tc, clk_get_rate(tc->refclk), in tc_edp_stream_enable()
1381 1000 * tc->mode.clock); in tc_edp_stream_enable()
1386 ret = tc_set_common_video_mode(tc, &tc->mode); in tc_edp_stream_enable()
1390 ret = tc_set_edp_video_mode(tc, &tc->mode); in tc_edp_stream_enable()
1395 ret = tc_stream_clock_calc(tc); in tc_edp_stream_enable()
1400 if (drm_dp_enhanced_frame_cap(tc->link.dpcd)) in tc_edp_stream_enable()
1402 ret = regmap_write(tc->regmap, DP0CTL, value); in tc_edp_stream_enable()
1414 ret = regmap_write(tc->regmap, DP0CTL, value); in tc_edp_stream_enable()
1419 if (tc->input_connector_dsi) in tc_edp_stream_enable()
1420 return tc_dsi_rx_enable(tc); in tc_edp_stream_enable()
1422 return tc_dpi_rx_enable(tc); in tc_edp_stream_enable()
1425 static int tc_edp_stream_disable(struct tc_data *tc) in tc_edp_stream_disable() argument
1429 dev_dbg(tc->dev, "disable video stream\n"); in tc_edp_stream_disable()
1431 ret = regmap_update_bits(tc->regmap, DP0CTL, VID_EN, 0); in tc_edp_stream_disable()
1435 tc_pxl_pll_dis(tc); in tc_edp_stream_disable()
1445 struct tc_data *tc = bridge_to_tc(bridge); in tc_dpi_bridge_atomic_enable() local
1448 ret = tc_dpi_stream_enable(tc); in tc_dpi_bridge_atomic_enable()
1450 dev_err(tc->dev, "main link stream start error: %d\n", ret); in tc_dpi_bridge_atomic_enable()
1451 tc_main_link_disable(tc); in tc_dpi_bridge_atomic_enable()
1460 struct tc_data *tc = bridge_to_tc(bridge); in tc_dpi_bridge_atomic_disable() local
1463 ret = tc_dpi_stream_disable(tc); in tc_dpi_bridge_atomic_disable()
1465 dev_err(tc->dev, "main link stream stop error: %d\n", ret); in tc_dpi_bridge_atomic_disable()
1472 struct tc_data *tc = bridge_to_tc(bridge); in tc_edp_bridge_atomic_enable() local
1475 ret = tc_get_display_props(tc); in tc_edp_bridge_atomic_enable()
1477 dev_err(tc->dev, "failed to read display props: %d\n", ret); in tc_edp_bridge_atomic_enable()
1481 ret = tc_main_link_enable(tc); in tc_edp_bridge_atomic_enable()
1483 dev_err(tc->dev, "main link enable error: %d\n", ret); in tc_edp_bridge_atomic_enable()
1487 ret = tc_edp_stream_enable(tc); in tc_edp_bridge_atomic_enable()
1489 dev_err(tc->dev, "main link stream start error: %d\n", ret); in tc_edp_bridge_atomic_enable()
1490 tc_main_link_disable(tc); in tc_edp_bridge_atomic_enable()
1499 struct tc_data *tc = bridge_to_tc(bridge); in tc_edp_bridge_atomic_disable() local
1502 ret = tc_edp_stream_disable(tc); in tc_edp_bridge_atomic_disable()
1504 dev_err(tc->dev, "main link stream stop error: %d\n", ret); in tc_edp_bridge_atomic_disable()
1506 ret = tc_main_link_disable(tc); in tc_edp_bridge_atomic_disable()
1508 dev_err(tc->dev, "main link disable error: %d\n", ret); in tc_edp_bridge_atomic_disable()
1552 struct tc_data *tc = bridge_to_tc(bridge); in tc_edp_mode_valid() local
1561 avail = tc->link.num_lanes * tc->link.rate; in tc_edp_mode_valid()
1573 struct tc_data *tc = bridge_to_tc(bridge); in tc_bridge_mode_set() local
1575 drm_mode_copy(&tc->mode, mode); in tc_bridge_mode_set()
1581 struct tc_data *tc = bridge_to_tc(bridge); in tc_get_edid() local
1583 return drm_get_edid(connector, &tc->aux.ddc); in tc_get_edid()
1588 struct tc_data *tc = connector_to_tc(connector); in tc_connector_get_modes() local
1593 ret = tc_get_display_props(tc); in tc_connector_get_modes()
1595 dev_err(tc->dev, "failed to read display props: %d\n", ret); in tc_connector_get_modes()
1599 if (tc->panel_bridge) { in tc_connector_get_modes()
1600 num_modes = drm_bridge_get_modes(tc->panel_bridge, connector); in tc_connector_get_modes()
1605 edid = tc_get_edid(&tc->bridge, connector); in tc_connector_get_modes()
1618 struct tc_data *tc = bridge_to_tc(bridge); in tc_bridge_detect() local
1623 ret = regmap_read(tc->regmap, GPIOI, &val); in tc_bridge_detect()
1627 conn = val & BIT(tc->hpd_pin); in tc_bridge_detect()
1638 struct tc_data *tc = connector_to_tc(connector); in tc_connector_detect() local
1640 if (tc->hpd_pin >= 0) in tc_connector_detect()
1641 return tc_bridge_detect(&tc->bridge); in tc_connector_detect()
1643 if (tc->panel_bridge) in tc_connector_detect()
1661 struct tc_data *tc = bridge_to_tc(bridge); in tc_dpi_bridge_attach() local
1663 if (!tc->panel_bridge) in tc_dpi_bridge_attach()
1666 return drm_bridge_attach(tc->bridge.encoder, tc->panel_bridge, in tc_dpi_bridge_attach()
1667 &tc->bridge, flags); in tc_dpi_bridge_attach()
1674 struct tc_data *tc = bridge_to_tc(bridge); in tc_edp_bridge_attach() local
1678 if (tc->panel_bridge) { in tc_edp_bridge_attach()
1680 ret = drm_bridge_attach(tc->bridge.encoder, tc->panel_bridge, in tc_edp_bridge_attach()
1681 &tc->bridge, flags | DRM_BRIDGE_ATTACH_NO_CONNECTOR); in tc_edp_bridge_attach()
1689 tc->aux.drm_dev = drm; in tc_edp_bridge_attach()
1690 ret = drm_dp_aux_register(&tc->aux); in tc_edp_bridge_attach()
1695 drm_connector_helper_add(&tc->connector, &tc_connector_helper_funcs); in tc_edp_bridge_attach()
1696 ret = drm_connector_init(drm, &tc->connector, &tc_connector_funcs, tc->bridge.type); in tc_edp_bridge_attach()
1701 if (tc->hpd_pin >= 0) { in tc_edp_bridge_attach()
1702 if (tc->have_irq) in tc_edp_bridge_attach()
1703 tc->connector.polled = DRM_CONNECTOR_POLL_HPD; in tc_edp_bridge_attach()
1705 tc->connector.polled = DRM_CONNECTOR_POLL_CONNECT | in tc_edp_bridge_attach()
1709 drm_display_info_set_bus_formats(&tc->connector.display_info, in tc_edp_bridge_attach()
1711 tc->connector.display_info.bus_flags = in tc_edp_bridge_attach()
1715 drm_connector_attach_encoder(&tc->connector, tc->bridge.encoder); in tc_edp_bridge_attach()
1719 drm_dp_aux_unregister(&tc->aux); in tc_edp_bridge_attach()
1825 struct tc_data *tc = arg; in tc_irq_handler() local
1829 r = regmap_read(tc->regmap, INTSTS_G, &val); in tc_irq_handler()
1839 regmap_read(tc->regmap, SYSSTAT, &stat); in tc_irq_handler()
1841 dev_err(tc->dev, "syserr %x\n", stat); in tc_irq_handler()
1844 if (tc->hpd_pin >= 0 && tc->bridge.dev) { in tc_irq_handler()
1851 bool h = val & INT_GPIO_H(tc->hpd_pin); in tc_irq_handler()
1852 bool lc = val & INT_GPIO_LC(tc->hpd_pin); in tc_irq_handler()
1854 dev_dbg(tc->dev, "GPIO%d: %s %s\n", tc->hpd_pin, in tc_irq_handler()
1858 drm_kms_helper_hotplug_event(tc->bridge.dev); in tc_irq_handler()
1861 regmap_write(tc->regmap, INTSTS_G, val); in tc_irq_handler()
1866 static int tc_mipi_dsi_host_attach(struct tc_data *tc) in tc_mipi_dsi_host_attach() argument
1868 struct device *dev = tc->dev; in tc_mipi_dsi_host_attach()
1898 tc->dsi = dsi; in tc_mipi_dsi_host_attach()
1913 static int tc_probe_dpi_bridge_endpoint(struct tc_data *tc) in tc_probe_dpi_bridge_endpoint() argument
1915 struct device *dev = tc->dev; in tc_probe_dpi_bridge_endpoint()
1932 tc->panel_bridge = bridge; in tc_probe_dpi_bridge_endpoint()
1933 tc->bridge.type = DRM_MODE_CONNECTOR_DPI; in tc_probe_dpi_bridge_endpoint()
1934 tc->bridge.funcs = &tc_dpi_bridge_funcs; in tc_probe_dpi_bridge_endpoint()
1942 static int tc_probe_edp_bridge_endpoint(struct tc_data *tc) in tc_probe_edp_bridge_endpoint() argument
1944 struct device *dev = tc->dev; in tc_probe_edp_bridge_endpoint()
1960 tc->panel_bridge = panel_bridge; in tc_probe_edp_bridge_endpoint()
1961 tc->bridge.type = DRM_MODE_CONNECTOR_eDP; in tc_probe_edp_bridge_endpoint()
1963 tc->bridge.type = DRM_MODE_CONNECTOR_DisplayPort; in tc_probe_edp_bridge_endpoint()
1966 tc->bridge.funcs = &tc_edp_bridge_funcs; in tc_probe_edp_bridge_endpoint()
1967 if (tc->hpd_pin >= 0) in tc_probe_edp_bridge_endpoint()
1968 tc->bridge.ops |= DRM_BRIDGE_OP_DETECT; in tc_probe_edp_bridge_endpoint()
1969 tc->bridge.ops |= DRM_BRIDGE_OP_EDID; in tc_probe_edp_bridge_endpoint()
1974 static int tc_probe_bridge_endpoint(struct tc_data *tc) in tc_probe_bridge_endpoint() argument
1976 struct device *dev = tc->dev; in tc_probe_bridge_endpoint()
2010 tc->input_connector_dsi = false; in tc_probe_bridge_endpoint()
2011 return tc_probe_edp_bridge_endpoint(tc); in tc_probe_bridge_endpoint()
2013 tc->input_connector_dsi = true; in tc_probe_bridge_endpoint()
2014 return tc_probe_dpi_bridge_endpoint(tc); in tc_probe_bridge_endpoint()
2016 tc->input_connector_dsi = true; in tc_probe_bridge_endpoint()
2017 return tc_probe_edp_bridge_endpoint(tc); in tc_probe_bridge_endpoint()
2035 struct tc_data *tc; in tc_probe() local
2038 tc = devm_kzalloc(dev, sizeof(*tc), GFP_KERNEL); in tc_probe()
2039 if (!tc) in tc_probe()
2042 tc->dev = dev; in tc_probe()
2044 ret = tc_probe_bridge_endpoint(tc); in tc_probe()
2048 tc->refclk = devm_clk_get(dev, "ref"); in tc_probe()
2049 if (IS_ERR(tc->refclk)) { in tc_probe()
2050 ret = PTR_ERR(tc->refclk); in tc_probe()
2055 ret = clk_prepare_enable(tc->refclk); in tc_probe()
2059 ret = devm_add_action_or_reset(dev, tc_clk_disable, tc->refclk); in tc_probe()
2067 tc->sd_gpio = devm_gpiod_get_optional(dev, "shutdown", GPIOD_OUT_HIGH); in tc_probe()
2068 if (IS_ERR(tc->sd_gpio)) in tc_probe()
2069 return PTR_ERR(tc->sd_gpio); in tc_probe()
2071 if (tc->sd_gpio) { in tc_probe()
2072 gpiod_set_value_cansleep(tc->sd_gpio, 0); in tc_probe()
2077 tc->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); in tc_probe()
2078 if (IS_ERR(tc->reset_gpio)) in tc_probe()
2079 return PTR_ERR(tc->reset_gpio); in tc_probe()
2081 if (tc->reset_gpio) { in tc_probe()
2082 gpiod_set_value_cansleep(tc->reset_gpio, 1); in tc_probe()
2086 tc->regmap = devm_regmap_init_i2c(client, &tc_regmap_config); in tc_probe()
2087 if (IS_ERR(tc->regmap)) { in tc_probe()
2088 ret = PTR_ERR(tc->regmap); in tc_probe()
2094 &tc->hpd_pin); in tc_probe()
2096 tc->hpd_pin = -ENODEV; in tc_probe()
2098 if (tc->hpd_pin < 0 || tc->hpd_pin > 1) { in tc_probe()
2106 regmap_write(tc->regmap, INTCTL_G, INT_SYSERR); in tc_probe()
2111 "tc358767-irq", tc); in tc_probe()
2117 tc->have_irq = true; in tc_probe()
2120 ret = regmap_read(tc->regmap, TC_IDREG, &tc->rev); in tc_probe()
2122 dev_err(tc->dev, "can not read device ID: %d\n", ret); in tc_probe()
2126 if ((tc->rev != 0x6601) && (tc->rev != 0x6603)) { in tc_probe()
2127 dev_err(tc->dev, "invalid device ID: 0x%08x\n", tc->rev); in tc_probe()
2131 tc->assr = (tc->rev == 0x6601); /* Enable ASSR for eDP panels */ in tc_probe()
2133 if (!tc->reset_gpio) { in tc_probe()
2140 regmap_update_bits(tc->regmap, SYSRSTENB, in tc_probe()
2143 regmap_update_bits(tc->regmap, SYSRSTENB, in tc_probe()
2149 if (tc->hpd_pin >= 0) { in tc_probe()
2150 u32 lcnt_reg = tc->hpd_pin == 0 ? INT_GP0_LCNT : INT_GP1_LCNT; in tc_probe()
2151 u32 h_lc = INT_GPIO_H(tc->hpd_pin) | INT_GPIO_LC(tc->hpd_pin); in tc_probe()
2154 regmap_write(tc->regmap, lcnt_reg, in tc_probe()
2155 clk_get_rate(tc->refclk) * 2 / 1000); in tc_probe()
2157 regmap_write(tc->regmap, GPIOM, BIT(tc->hpd_pin)); in tc_probe()
2159 if (tc->have_irq) { in tc_probe()
2161 regmap_update_bits(tc->regmap, INTCTL_G, h_lc, h_lc); in tc_probe()
2165 if (tc->bridge.type != DRM_MODE_CONNECTOR_DPI) { /* (e)DP output */ in tc_probe()
2166 ret = tc_aux_link_setup(tc); in tc_probe()
2171 tc->bridge.of_node = dev->of_node; in tc_probe()
2172 drm_bridge_add(&tc->bridge); in tc_probe()
2174 i2c_set_clientdata(client, tc); in tc_probe()
2176 if (tc->input_connector_dsi) { /* DSI input */ in tc_probe()
2177 ret = tc_mipi_dsi_host_attach(tc); in tc_probe()
2179 drm_bridge_remove(&tc->bridge); in tc_probe()
2189 struct tc_data *tc = i2c_get_clientdata(client); in tc_remove() local
2191 drm_bridge_remove(&tc->bridge); in tc_remove()