Lines Matching refs:gpu
39 int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value) in etnaviv_gpu_get_param() argument
41 struct etnaviv_drm_private *priv = gpu->drm->dev_private; in etnaviv_gpu_get_param()
45 *value = gpu->identity.model; in etnaviv_gpu_get_param()
49 *value = gpu->identity.revision; in etnaviv_gpu_get_param()
53 *value = gpu->identity.features; in etnaviv_gpu_get_param()
57 *value = gpu->identity.minor_features0; in etnaviv_gpu_get_param()
61 *value = gpu->identity.minor_features1; in etnaviv_gpu_get_param()
65 *value = gpu->identity.minor_features2; in etnaviv_gpu_get_param()
69 *value = gpu->identity.minor_features3; in etnaviv_gpu_get_param()
73 *value = gpu->identity.minor_features4; in etnaviv_gpu_get_param()
77 *value = gpu->identity.minor_features5; in etnaviv_gpu_get_param()
81 *value = gpu->identity.minor_features6; in etnaviv_gpu_get_param()
85 *value = gpu->identity.minor_features7; in etnaviv_gpu_get_param()
89 *value = gpu->identity.minor_features8; in etnaviv_gpu_get_param()
93 *value = gpu->identity.minor_features9; in etnaviv_gpu_get_param()
97 *value = gpu->identity.minor_features10; in etnaviv_gpu_get_param()
101 *value = gpu->identity.minor_features11; in etnaviv_gpu_get_param()
105 *value = gpu->identity.stream_count; in etnaviv_gpu_get_param()
109 *value = gpu->identity.register_max; in etnaviv_gpu_get_param()
113 *value = gpu->identity.thread_count; in etnaviv_gpu_get_param()
117 *value = gpu->identity.vertex_cache_size; in etnaviv_gpu_get_param()
121 *value = gpu->identity.shader_core_count; in etnaviv_gpu_get_param()
125 *value = gpu->identity.pixel_pipes; in etnaviv_gpu_get_param()
129 *value = gpu->identity.vertex_output_buffer_size; in etnaviv_gpu_get_param()
133 *value = gpu->identity.buffer_size; in etnaviv_gpu_get_param()
137 *value = gpu->identity.instruction_count; in etnaviv_gpu_get_param()
141 *value = gpu->identity.num_constants; in etnaviv_gpu_get_param()
145 *value = gpu->identity.varyings_count; in etnaviv_gpu_get_param()
156 *value = gpu->identity.product_id; in etnaviv_gpu_get_param()
160 *value = gpu->identity.customer_id; in etnaviv_gpu_get_param()
164 *value = gpu->identity.eco_id; in etnaviv_gpu_get_param()
168 DBG("%s: invalid param: %u", dev_name(gpu->dev), param); in etnaviv_gpu_get_param()
176 #define etnaviv_is_model_rev(gpu, mod, rev) \ argument
177 ((gpu)->identity.model == chipModel_##mod && \
178 (gpu)->identity.revision == rev)
182 static void etnaviv_hw_specs(struct etnaviv_gpu *gpu) in etnaviv_hw_specs() argument
184 if (gpu->identity.minor_features0 & in etnaviv_hw_specs()
189 specs[0] = gpu_read(gpu, VIVS_HI_CHIP_SPECS); in etnaviv_hw_specs()
190 specs[1] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_2); in etnaviv_hw_specs()
191 specs[2] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_3); in etnaviv_hw_specs()
192 specs[3] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_4); in etnaviv_hw_specs()
194 gpu->identity.stream_count = etnaviv_field(specs[0], in etnaviv_hw_specs()
196 gpu->identity.register_max = etnaviv_field(specs[0], in etnaviv_hw_specs()
198 gpu->identity.thread_count = etnaviv_field(specs[0], in etnaviv_hw_specs()
200 gpu->identity.vertex_cache_size = etnaviv_field(specs[0], in etnaviv_hw_specs()
202 gpu->identity.shader_core_count = etnaviv_field(specs[0], in etnaviv_hw_specs()
204 gpu->identity.pixel_pipes = etnaviv_field(specs[0], in etnaviv_hw_specs()
206 gpu->identity.vertex_output_buffer_size = in etnaviv_hw_specs()
210 gpu->identity.buffer_size = etnaviv_field(specs[1], in etnaviv_hw_specs()
212 gpu->identity.instruction_count = etnaviv_field(specs[1], in etnaviv_hw_specs()
214 gpu->identity.num_constants = etnaviv_field(specs[1], in etnaviv_hw_specs()
217 gpu->identity.varyings_count = etnaviv_field(specs[2], in etnaviv_hw_specs()
224 gpu->identity.stream_count = streams; in etnaviv_hw_specs()
228 if (gpu->identity.stream_count == 0) { in etnaviv_hw_specs()
229 if (gpu->identity.model >= 0x1000) in etnaviv_hw_specs()
230 gpu->identity.stream_count = 4; in etnaviv_hw_specs()
232 gpu->identity.stream_count = 1; in etnaviv_hw_specs()
236 if (gpu->identity.register_max) in etnaviv_hw_specs()
237 gpu->identity.register_max = 1 << gpu->identity.register_max; in etnaviv_hw_specs()
238 else if (gpu->identity.model == chipModel_GC400) in etnaviv_hw_specs()
239 gpu->identity.register_max = 32; in etnaviv_hw_specs()
241 gpu->identity.register_max = 64; in etnaviv_hw_specs()
244 if (gpu->identity.thread_count) in etnaviv_hw_specs()
245 gpu->identity.thread_count = 1 << gpu->identity.thread_count; in etnaviv_hw_specs()
246 else if (gpu->identity.model == chipModel_GC400) in etnaviv_hw_specs()
247 gpu->identity.thread_count = 64; in etnaviv_hw_specs()
248 else if (gpu->identity.model == chipModel_GC500 || in etnaviv_hw_specs()
249 gpu->identity.model == chipModel_GC530) in etnaviv_hw_specs()
250 gpu->identity.thread_count = 128; in etnaviv_hw_specs()
252 gpu->identity.thread_count = 256; in etnaviv_hw_specs()
254 if (gpu->identity.vertex_cache_size == 0) in etnaviv_hw_specs()
255 gpu->identity.vertex_cache_size = 8; in etnaviv_hw_specs()
257 if (gpu->identity.shader_core_count == 0) { in etnaviv_hw_specs()
258 if (gpu->identity.model >= 0x1000) in etnaviv_hw_specs()
259 gpu->identity.shader_core_count = 2; in etnaviv_hw_specs()
261 gpu->identity.shader_core_count = 1; in etnaviv_hw_specs()
264 if (gpu->identity.pixel_pipes == 0) in etnaviv_hw_specs()
265 gpu->identity.pixel_pipes = 1; in etnaviv_hw_specs()
268 if (gpu->identity.vertex_output_buffer_size) { in etnaviv_hw_specs()
269 gpu->identity.vertex_output_buffer_size = in etnaviv_hw_specs()
270 1 << gpu->identity.vertex_output_buffer_size; in etnaviv_hw_specs()
271 } else if (gpu->identity.model == chipModel_GC400) { in etnaviv_hw_specs()
272 if (gpu->identity.revision < 0x4000) in etnaviv_hw_specs()
273 gpu->identity.vertex_output_buffer_size = 512; in etnaviv_hw_specs()
274 else if (gpu->identity.revision < 0x4200) in etnaviv_hw_specs()
275 gpu->identity.vertex_output_buffer_size = 256; in etnaviv_hw_specs()
277 gpu->identity.vertex_output_buffer_size = 128; in etnaviv_hw_specs()
279 gpu->identity.vertex_output_buffer_size = 512; in etnaviv_hw_specs()
282 switch (gpu->identity.instruction_count) { in etnaviv_hw_specs()
284 if (etnaviv_is_model_rev(gpu, GC2000, 0x5108) || in etnaviv_hw_specs()
285 gpu->identity.model == chipModel_GC880) in etnaviv_hw_specs()
286 gpu->identity.instruction_count = 512; in etnaviv_hw_specs()
288 gpu->identity.instruction_count = 256; in etnaviv_hw_specs()
292 gpu->identity.instruction_count = 1024; in etnaviv_hw_specs()
296 gpu->identity.instruction_count = 2048; in etnaviv_hw_specs()
300 gpu->identity.instruction_count = 256; in etnaviv_hw_specs()
304 if (gpu->identity.num_constants == 0) in etnaviv_hw_specs()
305 gpu->identity.num_constants = 168; in etnaviv_hw_specs()
307 if (gpu->identity.varyings_count == 0) { in etnaviv_hw_specs()
308 if (gpu->identity.minor_features1 & chipMinorFeatures1_HALTI0) in etnaviv_hw_specs()
309 gpu->identity.varyings_count = 12; in etnaviv_hw_specs()
311 gpu->identity.varyings_count = 8; in etnaviv_hw_specs()
318 if (etnaviv_is_model_rev(gpu, GC5000, 0x5434) || in etnaviv_hw_specs()
319 etnaviv_is_model_rev(gpu, GC4000, 0x5222) || in etnaviv_hw_specs()
320 etnaviv_is_model_rev(gpu, GC4000, 0x5245) || in etnaviv_hw_specs()
321 etnaviv_is_model_rev(gpu, GC4000, 0x5208) || in etnaviv_hw_specs()
322 etnaviv_is_model_rev(gpu, GC3000, 0x5435) || in etnaviv_hw_specs()
323 etnaviv_is_model_rev(gpu, GC2200, 0x5244) || in etnaviv_hw_specs()
324 etnaviv_is_model_rev(gpu, GC2100, 0x5108) || in etnaviv_hw_specs()
325 etnaviv_is_model_rev(gpu, GC2000, 0x5108) || in etnaviv_hw_specs()
326 etnaviv_is_model_rev(gpu, GC1500, 0x5246) || in etnaviv_hw_specs()
327 etnaviv_is_model_rev(gpu, GC880, 0x5107) || in etnaviv_hw_specs()
328 etnaviv_is_model_rev(gpu, GC880, 0x5106)) in etnaviv_hw_specs()
329 gpu->identity.varyings_count -= 1; in etnaviv_hw_specs()
332 static void etnaviv_hw_identify(struct etnaviv_gpu *gpu) in etnaviv_hw_identify() argument
336 chipIdentity = gpu_read(gpu, VIVS_HI_CHIP_IDENTITY); in etnaviv_hw_identify()
340 gpu->identity.model = chipModel_GC500; in etnaviv_hw_identify()
341 gpu->identity.revision = etnaviv_field(chipIdentity, in etnaviv_hw_identify()
344 u32 chipDate = gpu_read(gpu, VIVS_HI_CHIP_DATE); in etnaviv_hw_identify()
346 gpu->identity.model = gpu_read(gpu, VIVS_HI_CHIP_MODEL); in etnaviv_hw_identify()
347 gpu->identity.revision = gpu_read(gpu, VIVS_HI_CHIP_REV); in etnaviv_hw_identify()
348 gpu->identity.customer_id = gpu_read(gpu, VIVS_HI_CHIP_CUSTOMER_ID); in etnaviv_hw_identify()
354 if (!etnaviv_is_model_rev(gpu, GC600, 0x19)) { in etnaviv_hw_identify()
355 gpu->identity.product_id = gpu_read(gpu, VIVS_HI_CHIP_PRODUCT_ID); in etnaviv_hw_identify()
356 gpu->identity.eco_id = gpu_read(gpu, VIVS_HI_CHIP_ECO_ID); in etnaviv_hw_identify()
365 if ((gpu->identity.model & 0xff00) == 0x0400 && in etnaviv_hw_identify()
366 gpu->identity.model != chipModel_GC420) { in etnaviv_hw_identify()
367 gpu->identity.model = gpu->identity.model & 0x0400; in etnaviv_hw_identify()
371 if (etnaviv_is_model_rev(gpu, GC300, 0x2201)) { in etnaviv_hw_identify()
372 u32 chipTime = gpu_read(gpu, VIVS_HI_CHIP_TIME); in etnaviv_hw_identify()
379 gpu->identity.revision = 0x1051; in etnaviv_hw_identify()
390 if (etnaviv_is_model_rev(gpu, GC2000, 0xffff5450)) { in etnaviv_hw_identify()
391 gpu->identity.model = chipModel_GC3000; in etnaviv_hw_identify()
392 gpu->identity.revision &= 0xffff; in etnaviv_hw_identify()
395 if (etnaviv_is_model_rev(gpu, GC1000, 0x5037) && (chipDate == 0x20120617)) in etnaviv_hw_identify()
396 gpu->identity.eco_id = 1; in etnaviv_hw_identify()
398 if (etnaviv_is_model_rev(gpu, GC320, 0x5303) && (chipDate == 0x20140511)) in etnaviv_hw_identify()
399 gpu->identity.eco_id = 1; in etnaviv_hw_identify()
402 dev_info(gpu->dev, "model: GC%x, revision: %x\n", in etnaviv_hw_identify()
403 gpu->identity.model, gpu->identity.revision); in etnaviv_hw_identify()
405 gpu->idle_mask = ~VIVS_HI_IDLE_STATE_AXI_LP; in etnaviv_hw_identify()
410 if (etnaviv_fill_identity_from_hwdb(gpu)) in etnaviv_hw_identify()
413 gpu->identity.features = gpu_read(gpu, VIVS_HI_CHIP_FEATURE); in etnaviv_hw_identify()
416 if (gpu->identity.model == chipModel_GC700) in etnaviv_hw_identify()
417 gpu->identity.features &= ~chipFeatures_FAST_CLEAR; in etnaviv_hw_identify()
420 if ((gpu->identity.model == chipModel_GC500 && in etnaviv_hw_identify()
421 gpu->identity.revision <= 2) || in etnaviv_hw_identify()
422 gpu->identity.model == chipModel_GC300) in etnaviv_hw_identify()
423 gpu->identity.features |= chipFeatures_PIPE_2D; in etnaviv_hw_identify()
425 if ((gpu->identity.model == chipModel_GC500 && in etnaviv_hw_identify()
426 gpu->identity.revision < 2) || in etnaviv_hw_identify()
427 (gpu->identity.model == chipModel_GC300 && in etnaviv_hw_identify()
428 gpu->identity.revision < 0x2000)) { in etnaviv_hw_identify()
434 gpu->identity.minor_features0 = 0; in etnaviv_hw_identify()
435 gpu->identity.minor_features1 = 0; in etnaviv_hw_identify()
436 gpu->identity.minor_features2 = 0; in etnaviv_hw_identify()
437 gpu->identity.minor_features3 = 0; in etnaviv_hw_identify()
438 gpu->identity.minor_features4 = 0; in etnaviv_hw_identify()
439 gpu->identity.minor_features5 = 0; in etnaviv_hw_identify()
441 gpu->identity.minor_features0 = in etnaviv_hw_identify()
442 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_0); in etnaviv_hw_identify()
444 if (gpu->identity.minor_features0 & in etnaviv_hw_identify()
446 gpu->identity.minor_features1 = in etnaviv_hw_identify()
447 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_1); in etnaviv_hw_identify()
448 gpu->identity.minor_features2 = in etnaviv_hw_identify()
449 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_2); in etnaviv_hw_identify()
450 gpu->identity.minor_features3 = in etnaviv_hw_identify()
451 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_3); in etnaviv_hw_identify()
452 gpu->identity.minor_features4 = in etnaviv_hw_identify()
453 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_4); in etnaviv_hw_identify()
454 gpu->identity.minor_features5 = in etnaviv_hw_identify()
455 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_5); in etnaviv_hw_identify()
459 if (gpu->identity.model == chipModel_GC600 || in etnaviv_hw_identify()
460 gpu->identity.model == chipModel_GC300) in etnaviv_hw_identify()
461 gpu->idle_mask = VIVS_HI_IDLE_STATE_TX | in etnaviv_hw_identify()
470 etnaviv_hw_specs(gpu); in etnaviv_hw_identify()
473 static void etnaviv_gpu_load_clock(struct etnaviv_gpu *gpu, u32 clock) in etnaviv_gpu_load_clock() argument
475 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock | in etnaviv_gpu_load_clock()
477 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock); in etnaviv_gpu_load_clock()
480 static void etnaviv_gpu_update_clock(struct etnaviv_gpu *gpu) in etnaviv_gpu_update_clock() argument
482 if (gpu->identity.minor_features2 & in etnaviv_gpu_update_clock()
484 clk_set_rate(gpu->clk_core, in etnaviv_gpu_update_clock()
485 gpu->base_rate_core >> gpu->freq_scale); in etnaviv_gpu_update_clock()
486 clk_set_rate(gpu->clk_shader, in etnaviv_gpu_update_clock()
487 gpu->base_rate_shader >> gpu->freq_scale); in etnaviv_gpu_update_clock()
489 unsigned int fscale = 1 << (6 - gpu->freq_scale); in etnaviv_gpu_update_clock()
490 u32 clock = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); in etnaviv_gpu_update_clock()
494 etnaviv_gpu_load_clock(gpu, clock); in etnaviv_gpu_update_clock()
498 static int etnaviv_hw_reset(struct etnaviv_gpu *gpu) in etnaviv_hw_reset() argument
509 unsigned int fscale = 1 << (6 - gpu->freq_scale); in etnaviv_hw_reset()
511 etnaviv_gpu_load_clock(gpu, control); in etnaviv_hw_reset()
515 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); in etnaviv_hw_reset()
517 if (gpu->sec_mode == ETNA_SEC_KERNEL) { in etnaviv_hw_reset()
518 gpu_write(gpu, VIVS_MMUv2_AHB_CONTROL, in etnaviv_hw_reset()
523 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); in etnaviv_hw_reset()
531 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); in etnaviv_hw_reset()
535 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); in etnaviv_hw_reset()
538 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE); in etnaviv_hw_reset()
542 dev_dbg(gpu->dev, "FE is not idle\n"); in etnaviv_hw_reset()
547 control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); in etnaviv_hw_reset()
552 dev_dbg(gpu->dev, "GPU is not idle\n"); in etnaviv_hw_reset()
558 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); in etnaviv_hw_reset()
565 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE); in etnaviv_hw_reset()
566 control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); in etnaviv_hw_reset()
568 dev_err(gpu->dev, "GPU failed to reset: FE %sidle, 3D %sidle, 2D %sidle\n", in etnaviv_hw_reset()
577 etnaviv_gpu_update_clock(gpu); in etnaviv_hw_reset()
579 gpu->fe_running = false; in etnaviv_hw_reset()
580 gpu->exec_state = -1; in etnaviv_hw_reset()
581 if (gpu->mmu_context) in etnaviv_hw_reset()
582 etnaviv_iommu_context_put(gpu->mmu_context); in etnaviv_hw_reset()
583 gpu->mmu_context = NULL; in etnaviv_hw_reset()
588 static void etnaviv_gpu_enable_mlcg(struct etnaviv_gpu *gpu) in etnaviv_gpu_enable_mlcg() argument
593 ppc = gpu_read_power(gpu, VIVS_PM_POWER_CONTROLS); in etnaviv_gpu_enable_mlcg()
597 if (gpu->identity.revision == 0x4301 || in etnaviv_gpu_enable_mlcg()
598 gpu->identity.revision == 0x4302) in etnaviv_gpu_enable_mlcg()
601 gpu_write_power(gpu, VIVS_PM_POWER_CONTROLS, ppc); in etnaviv_gpu_enable_mlcg()
603 pmc = gpu_read_power(gpu, VIVS_PM_MODULE_CONTROLS); in etnaviv_gpu_enable_mlcg()
606 if (gpu->identity.model >= chipModel_GC400 && in etnaviv_gpu_enable_mlcg()
607 gpu->identity.model != chipModel_GC420 && in etnaviv_gpu_enable_mlcg()
608 !(gpu->identity.minor_features3 & chipMinorFeatures3_BUG_FIXES12)) in etnaviv_gpu_enable_mlcg()
615 if (gpu->identity.revision < 0x5000 && in etnaviv_gpu_enable_mlcg()
616 gpu->identity.minor_features0 & chipMinorFeatures0_HZ && in etnaviv_gpu_enable_mlcg()
617 !(gpu->identity.minor_features1 & in etnaviv_gpu_enable_mlcg()
621 if (gpu->identity.revision < 0x5422) in etnaviv_gpu_enable_mlcg()
625 if (etnaviv_is_model_rev(gpu, GC4000, 0x5222) || in etnaviv_gpu_enable_mlcg()
626 etnaviv_is_model_rev(gpu, GC2000, 0x5108) || in etnaviv_gpu_enable_mlcg()
627 etnaviv_is_model_rev(gpu, GC2000, 0x6202) || in etnaviv_gpu_enable_mlcg()
628 etnaviv_is_model_rev(gpu, GC2000, 0x6203)) in etnaviv_gpu_enable_mlcg()
632 if (etnaviv_is_model_rev(gpu, GC7000, 0x6202)) in etnaviv_gpu_enable_mlcg()
639 gpu_write_power(gpu, VIVS_PM_MODULE_CONTROLS, pmc); in etnaviv_gpu_enable_mlcg()
642 void etnaviv_gpu_start_fe(struct etnaviv_gpu *gpu, u32 address, u16 prefetch) in etnaviv_gpu_start_fe() argument
644 gpu_write(gpu, VIVS_FE_COMMAND_ADDRESS, address); in etnaviv_gpu_start_fe()
645 gpu_write(gpu, VIVS_FE_COMMAND_CONTROL, in etnaviv_gpu_start_fe()
649 if (gpu->sec_mode == ETNA_SEC_KERNEL) { in etnaviv_gpu_start_fe()
650 gpu_write(gpu, VIVS_MMUv2_SEC_COMMAND_CONTROL, in etnaviv_gpu_start_fe()
655 gpu->fe_running = true; in etnaviv_gpu_start_fe()
658 static void etnaviv_gpu_start_fe_idleloop(struct etnaviv_gpu *gpu, in etnaviv_gpu_start_fe_idleloop() argument
665 etnaviv_iommu_restore(gpu, context); in etnaviv_gpu_start_fe_idleloop()
668 prefetch = etnaviv_buffer_init(gpu); in etnaviv_gpu_start_fe_idleloop()
669 address = etnaviv_cmdbuf_get_va(&gpu->buffer, in etnaviv_gpu_start_fe_idleloop()
670 &gpu->mmu_context->cmdbuf_mapping); in etnaviv_gpu_start_fe_idleloop()
672 etnaviv_gpu_start_fe(gpu, address, prefetch); in etnaviv_gpu_start_fe_idleloop()
675 static void etnaviv_gpu_setup_pulse_eater(struct etnaviv_gpu *gpu) in etnaviv_gpu_setup_pulse_eater() argument
683 if (etnaviv_is_model_rev(gpu, GC4000, 0x5208) || in etnaviv_gpu_setup_pulse_eater()
684 etnaviv_is_model_rev(gpu, GC4000, 0x5222)) { in etnaviv_gpu_setup_pulse_eater()
689 if (etnaviv_is_model_rev(gpu, GC1000, 0x5039) || in etnaviv_gpu_setup_pulse_eater()
690 etnaviv_is_model_rev(gpu, GC1000, 0x5040)) { in etnaviv_gpu_setup_pulse_eater()
695 if ((gpu->identity.revision > 0x5420) && in etnaviv_gpu_setup_pulse_eater()
696 (gpu->identity.features & chipFeatures_PIPE_3D)) in etnaviv_gpu_setup_pulse_eater()
699 pulse_eater = gpu_read_power(gpu, VIVS_PM_PULSE_EATER); in etnaviv_gpu_setup_pulse_eater()
703 gpu_write_power(gpu, VIVS_PM_PULSE_EATER, pulse_eater); in etnaviv_gpu_setup_pulse_eater()
706 static void etnaviv_gpu_hw_init(struct etnaviv_gpu *gpu) in etnaviv_gpu_hw_init() argument
708 if ((etnaviv_is_model_rev(gpu, GC320, 0x5007) || in etnaviv_gpu_hw_init()
709 etnaviv_is_model_rev(gpu, GC320, 0x5220)) && in etnaviv_gpu_hw_init()
710 gpu_read(gpu, VIVS_HI_CHIP_TIME) != 0x2062400) { in etnaviv_gpu_hw_init()
713 mc_memory_debug = gpu_read(gpu, VIVS_MC_DEBUG_MEMORY) & ~0xff; in etnaviv_gpu_hw_init()
715 if (gpu->identity.revision == 0x5007) in etnaviv_gpu_hw_init()
720 gpu_write(gpu, VIVS_MC_DEBUG_MEMORY, mc_memory_debug); in etnaviv_gpu_hw_init()
724 etnaviv_gpu_enable_mlcg(gpu); in etnaviv_gpu_hw_init()
730 gpu_write(gpu, VIVS_HI_AXI_CONFIG, in etnaviv_gpu_hw_init()
735 if (etnaviv_is_model_rev(gpu, GC2000, 0x5108)) { in etnaviv_gpu_hw_init()
736 u32 bus_config = gpu_read(gpu, VIVS_MC_BUS_CONFIG); in etnaviv_gpu_hw_init()
741 gpu_write(gpu, VIVS_MC_BUS_CONFIG, bus_config); in etnaviv_gpu_hw_init()
744 if (gpu->sec_mode == ETNA_SEC_KERNEL) { in etnaviv_gpu_hw_init()
745 u32 val = gpu_read(gpu, VIVS_MMUv2_AHB_CONTROL); in etnaviv_gpu_hw_init()
747 gpu_write(gpu, VIVS_MMUv2_AHB_CONTROL, val); in etnaviv_gpu_hw_init()
751 etnaviv_gpu_setup_pulse_eater(gpu); in etnaviv_gpu_hw_init()
753 gpu_write(gpu, VIVS_HI_INTR_ENBL, ~0U); in etnaviv_gpu_hw_init()
756 int etnaviv_gpu_init(struct etnaviv_gpu *gpu) in etnaviv_gpu_init() argument
758 struct etnaviv_drm_private *priv = gpu->drm->dev_private; in etnaviv_gpu_init()
762 ret = pm_runtime_get_sync(gpu->dev); in etnaviv_gpu_init()
764 dev_err(gpu->dev, "Failed to enable GPU power domain\n"); in etnaviv_gpu_init()
768 etnaviv_hw_identify(gpu); in etnaviv_gpu_init()
770 if (gpu->identity.model == 0) { in etnaviv_gpu_init()
771 dev_err(gpu->dev, "Unknown GPU model\n"); in etnaviv_gpu_init()
776 if (gpu->identity.nn_core_count > 0) in etnaviv_gpu_init()
777 dev_warn(gpu->dev, "etnaviv has been instantiated on a NPU, " in etnaviv_gpu_init()
781 if (gpu->identity.features & chipFeatures_PIPE_VG && in etnaviv_gpu_init()
782 gpu->identity.features & chipFeatures_FE20) { in etnaviv_gpu_init()
783 dev_info(gpu->dev, "Ignoring GPU with VG and FE2.0\n"); in etnaviv_gpu_init()
792 if ((gpu->identity.minor_features7 & chipMinorFeatures7_BIT_SECURITY) && in etnaviv_gpu_init()
793 (gpu->identity.minor_features10 & chipMinorFeatures10_SECURITY_AHB)) in etnaviv_gpu_init()
794 gpu->sec_mode = ETNA_SEC_KERNEL; in etnaviv_gpu_init()
796 ret = etnaviv_hw_reset(gpu); in etnaviv_gpu_init()
798 dev_err(gpu->dev, "GPU reset failed\n"); in etnaviv_gpu_init()
802 ret = etnaviv_iommu_global_init(gpu); in etnaviv_gpu_init()
811 if (dma_addressing_limited(gpu->dev)) in etnaviv_gpu_init()
815 ret = etnaviv_cmdbuf_init(priv->cmdbuf_suballoc, &gpu->buffer, in etnaviv_gpu_init()
818 dev_err(gpu->dev, "could not create command buffer\n"); in etnaviv_gpu_init()
832 cmdbuf_paddr = ALIGN_DOWN(etnaviv_cmdbuf_get_pa(&gpu->buffer), SZ_128M); in etnaviv_gpu_init()
834 if (!(gpu->identity.features & chipFeatures_PIPE_3D) || in etnaviv_gpu_init()
835 (gpu->identity.minor_features0 & chipMinorFeatures0_MC20)) { in etnaviv_gpu_init()
841 dev_info(gpu->dev, in etnaviv_gpu_init()
843 gpu->identity.features &= ~chipFeatures_FAST_CLEAR; in etnaviv_gpu_init()
848 spin_lock_init(&gpu->event_spinlock); in etnaviv_gpu_init()
849 init_completion(&gpu->event_free); in etnaviv_gpu_init()
850 bitmap_zero(gpu->event_bitmap, ETNA_NR_EVENTS); in etnaviv_gpu_init()
851 for (i = 0; i < ARRAY_SIZE(gpu->event); i++) in etnaviv_gpu_init()
852 complete(&gpu->event_free); in etnaviv_gpu_init()
855 mutex_lock(&gpu->lock); in etnaviv_gpu_init()
856 etnaviv_gpu_hw_init(gpu); in etnaviv_gpu_init()
857 mutex_unlock(&gpu->lock); in etnaviv_gpu_init()
859 pm_runtime_mark_last_busy(gpu->dev); in etnaviv_gpu_init()
860 pm_runtime_put_autosuspend(gpu->dev); in etnaviv_gpu_init()
862 gpu->initialized = true; in etnaviv_gpu_init()
867 pm_runtime_mark_last_busy(gpu->dev); in etnaviv_gpu_init()
869 pm_runtime_put_autosuspend(gpu->dev); in etnaviv_gpu_init()
880 static void verify_dma(struct etnaviv_gpu *gpu, struct dma_debug *debug) in verify_dma() argument
884 debug->address[0] = gpu_read(gpu, VIVS_FE_DMA_ADDRESS); in verify_dma()
885 debug->state[0] = gpu_read(gpu, VIVS_FE_DMA_DEBUG_STATE); in verify_dma()
888 debug->address[1] = gpu_read(gpu, VIVS_FE_DMA_ADDRESS); in verify_dma()
889 debug->state[1] = gpu_read(gpu, VIVS_FE_DMA_DEBUG_STATE); in verify_dma()
899 int etnaviv_gpu_debugfs(struct etnaviv_gpu *gpu, struct seq_file *m) in etnaviv_gpu_debugfs() argument
905 seq_printf(m, "%s Status:\n", dev_name(gpu->dev)); in etnaviv_gpu_debugfs()
907 ret = pm_runtime_get_sync(gpu->dev); in etnaviv_gpu_debugfs()
911 dma_lo = gpu_read(gpu, VIVS_FE_DMA_LOW); in etnaviv_gpu_debugfs()
912 dma_hi = gpu_read(gpu, VIVS_FE_DMA_HIGH); in etnaviv_gpu_debugfs()
913 axi = gpu_read(gpu, VIVS_HI_AXI_STATUS); in etnaviv_gpu_debugfs()
914 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE); in etnaviv_gpu_debugfs()
916 verify_dma(gpu, &debug); in etnaviv_gpu_debugfs()
919 seq_printf(m, "\t model: 0x%x\n", gpu->identity.model); in etnaviv_gpu_debugfs()
920 seq_printf(m, "\t revision: 0x%x\n", gpu->identity.revision); in etnaviv_gpu_debugfs()
921 seq_printf(m, "\t product_id: 0x%x\n", gpu->identity.product_id); in etnaviv_gpu_debugfs()
922 seq_printf(m, "\t customer_id: 0x%x\n", gpu->identity.customer_id); in etnaviv_gpu_debugfs()
923 seq_printf(m, "\t eco_id: 0x%x\n", gpu->identity.eco_id); in etnaviv_gpu_debugfs()
927 gpu->identity.features); in etnaviv_gpu_debugfs()
929 gpu->identity.minor_features0); in etnaviv_gpu_debugfs()
931 gpu->identity.minor_features1); in etnaviv_gpu_debugfs()
933 gpu->identity.minor_features2); in etnaviv_gpu_debugfs()
935 gpu->identity.minor_features3); in etnaviv_gpu_debugfs()
937 gpu->identity.minor_features4); in etnaviv_gpu_debugfs()
939 gpu->identity.minor_features5); in etnaviv_gpu_debugfs()
941 gpu->identity.minor_features6); in etnaviv_gpu_debugfs()
943 gpu->identity.minor_features7); in etnaviv_gpu_debugfs()
945 gpu->identity.minor_features8); in etnaviv_gpu_debugfs()
947 gpu->identity.minor_features9); in etnaviv_gpu_debugfs()
949 gpu->identity.minor_features10); in etnaviv_gpu_debugfs()
951 gpu->identity.minor_features11); in etnaviv_gpu_debugfs()
955 gpu->identity.stream_count); in etnaviv_gpu_debugfs()
957 gpu->identity.register_max); in etnaviv_gpu_debugfs()
959 gpu->identity.thread_count); in etnaviv_gpu_debugfs()
961 gpu->identity.vertex_cache_size); in etnaviv_gpu_debugfs()
963 gpu->identity.shader_core_count); in etnaviv_gpu_debugfs()
965 gpu->identity.nn_core_count); in etnaviv_gpu_debugfs()
967 gpu->identity.pixel_pipes); in etnaviv_gpu_debugfs()
969 gpu->identity.vertex_output_buffer_size); in etnaviv_gpu_debugfs()
971 gpu->identity.buffer_size); in etnaviv_gpu_debugfs()
973 gpu->identity.instruction_count); in etnaviv_gpu_debugfs()
975 gpu->identity.num_constants); in etnaviv_gpu_debugfs()
977 gpu->identity.varyings_count); in etnaviv_gpu_debugfs()
981 idle |= ~gpu->idle_mask & ~VIVS_HI_IDLE_STATE_AXI_LP; in etnaviv_gpu_debugfs()
1023 if (gpu->identity.features & chipFeatures_DEBUG_MODE) { in etnaviv_gpu_debugfs()
1024 u32 read0 = gpu_read(gpu, VIVS_MC_DEBUG_READ0); in etnaviv_gpu_debugfs()
1025 u32 read1 = gpu_read(gpu, VIVS_MC_DEBUG_READ1); in etnaviv_gpu_debugfs()
1026 u32 write = gpu_read(gpu, VIVS_MC_DEBUG_WRITE); in etnaviv_gpu_debugfs()
1054 pm_runtime_mark_last_busy(gpu->dev); in etnaviv_gpu_debugfs()
1056 pm_runtime_put_autosuspend(gpu->dev); in etnaviv_gpu_debugfs()
1064 struct etnaviv_gpu *gpu = submit->gpu; in etnaviv_gpu_recover_hang() local
1069 dev_err(gpu->dev, "recover hung GPU!\n"); in etnaviv_gpu_recover_hang()
1079 dev_err(gpu->dev, "offending task: %s (%s)\n", comm, cmd); in etnaviv_gpu_recover_hang()
1084 if (pm_runtime_get_sync(gpu->dev) < 0) in etnaviv_gpu_recover_hang()
1087 mutex_lock(&gpu->lock); in etnaviv_gpu_recover_hang()
1089 etnaviv_hw_reset(gpu); in etnaviv_gpu_recover_hang()
1092 spin_lock(&gpu->event_spinlock); in etnaviv_gpu_recover_hang()
1093 for_each_set_bit(i, gpu->event_bitmap, ETNA_NR_EVENTS) in etnaviv_gpu_recover_hang()
1094 complete(&gpu->event_free); in etnaviv_gpu_recover_hang()
1095 bitmap_zero(gpu->event_bitmap, ETNA_NR_EVENTS); in etnaviv_gpu_recover_hang()
1096 spin_unlock(&gpu->event_spinlock); in etnaviv_gpu_recover_hang()
1098 etnaviv_gpu_hw_init(gpu); in etnaviv_gpu_recover_hang()
1100 mutex_unlock(&gpu->lock); in etnaviv_gpu_recover_hang()
1101 pm_runtime_mark_last_busy(gpu->dev); in etnaviv_gpu_recover_hang()
1103 pm_runtime_put_autosuspend(gpu->dev); in etnaviv_gpu_recover_hang()
1108 struct etnaviv_gpu *gpu; member
1126 return dev_name(f->gpu->dev); in etnaviv_fence_get_timeline_name()
1133 return (s32)(f->gpu->completed_fence - f->base.seqno) >= 0; in etnaviv_fence_signaled()
1150 static struct dma_fence *etnaviv_gpu_fence_alloc(struct etnaviv_gpu *gpu) in etnaviv_gpu_fence_alloc() argument
1158 lockdep_assert_held(&gpu->lock); in etnaviv_gpu_fence_alloc()
1164 f->gpu = gpu; in etnaviv_gpu_fence_alloc()
1166 dma_fence_init(&f->base, &etnaviv_fence_ops, &gpu->fence_spinlock, in etnaviv_gpu_fence_alloc()
1167 gpu->fence_context, ++gpu->next_fence); in etnaviv_gpu_fence_alloc()
1182 static int event_alloc(struct etnaviv_gpu *gpu, unsigned nr_events, in event_alloc() argument
1191 ret = wait_for_completion_timeout(&gpu->event_free, timeout); in event_alloc()
1194 dev_err(gpu->dev, "wait_for_completion_timeout failed"); in event_alloc()
1202 spin_lock(&gpu->event_spinlock); in event_alloc()
1205 int event = find_first_zero_bit(gpu->event_bitmap, ETNA_NR_EVENTS); in event_alloc()
1208 memset(&gpu->event[event], 0, sizeof(struct etnaviv_event)); in event_alloc()
1209 set_bit(event, gpu->event_bitmap); in event_alloc()
1212 spin_unlock(&gpu->event_spinlock); in event_alloc()
1218 complete(&gpu->event_free); in event_alloc()
1223 static void event_free(struct etnaviv_gpu *gpu, unsigned int event) in event_free() argument
1225 if (!test_bit(event, gpu->event_bitmap)) { in event_free()
1226 dev_warn(gpu->dev, "event %u is already marked as free", in event_free()
1229 clear_bit(event, gpu->event_bitmap); in event_free()
1230 complete(&gpu->event_free); in event_free()
1237 int etnaviv_gpu_wait_fence_interruptible(struct etnaviv_gpu *gpu, in etnaviv_gpu_wait_fence_interruptible() argument
1249 fence = xa_load(&gpu->user_fences, id); in etnaviv_gpu_wait_fence_interruptible()
1284 int etnaviv_gpu_wait_obj_inactive(struct etnaviv_gpu *gpu, in etnaviv_gpu_wait_obj_inactive() argument
1296 ret = wait_event_interruptible_timeout(gpu->fence_event, in etnaviv_gpu_wait_obj_inactive()
1307 static void sync_point_perfmon_sample(struct etnaviv_gpu *gpu, in sync_point_perfmon_sample() argument
1317 etnaviv_perfmon_process(gpu, pmr, submit->exec_state); in sync_point_perfmon_sample()
1321 static void sync_point_perfmon_sample_pre(struct etnaviv_gpu *gpu, in sync_point_perfmon_sample_pre() argument
1327 val = gpu_read_power(gpu, VIVS_PM_POWER_CONTROLS); in sync_point_perfmon_sample_pre()
1329 gpu_write_power(gpu, VIVS_PM_POWER_CONTROLS, val); in sync_point_perfmon_sample_pre()
1332 val = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); in sync_point_perfmon_sample_pre()
1334 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, val); in sync_point_perfmon_sample_pre()
1336 sync_point_perfmon_sample(gpu, event, ETNA_PM_PROCESS_PRE); in sync_point_perfmon_sample_pre()
1339 static void sync_point_perfmon_sample_post(struct etnaviv_gpu *gpu, in sync_point_perfmon_sample_post() argument
1346 sync_point_perfmon_sample(gpu, event, ETNA_PM_PROCESS_POST); in sync_point_perfmon_sample_post()
1355 val = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); in sync_point_perfmon_sample_post()
1357 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, val); in sync_point_perfmon_sample_post()
1360 val = gpu_read_power(gpu, VIVS_PM_POWER_CONTROLS); in sync_point_perfmon_sample_post()
1362 gpu_write_power(gpu, VIVS_PM_POWER_CONTROLS, val); in sync_point_perfmon_sample_post()
1369 struct etnaviv_gpu *gpu = submit->gpu; in etnaviv_gpu_submit() local
1375 ret = pm_runtime_get_sync(gpu->dev); in etnaviv_gpu_submit()
1377 pm_runtime_put_noidle(gpu->dev); in etnaviv_gpu_submit()
1393 ret = event_alloc(gpu, nr_events, event); in etnaviv_gpu_submit()
1396 pm_runtime_put_noidle(gpu->dev); in etnaviv_gpu_submit()
1400 mutex_lock(&gpu->lock); in etnaviv_gpu_submit()
1402 gpu_fence = etnaviv_gpu_fence_alloc(gpu); in etnaviv_gpu_submit()
1405 event_free(gpu, event[i]); in etnaviv_gpu_submit()
1410 if (!gpu->fe_running) in etnaviv_gpu_submit()
1411 etnaviv_gpu_start_fe_idleloop(gpu, submit->mmu_context); in etnaviv_gpu_submit()
1415 submit->prev_mmu_context = etnaviv_iommu_context_get(gpu->mmu_context); in etnaviv_gpu_submit()
1418 gpu->event[event[1]].sync_point = &sync_point_perfmon_sample_pre; in etnaviv_gpu_submit()
1420 gpu->event[event[1]].submit = submit; in etnaviv_gpu_submit()
1421 etnaviv_sync_point_queue(gpu, event[1]); in etnaviv_gpu_submit()
1424 gpu->event[event[0]].fence = gpu_fence; in etnaviv_gpu_submit()
1426 etnaviv_buffer_queue(gpu, submit->exec_state, submit->mmu_context, in etnaviv_gpu_submit()
1430 gpu->event[event[2]].sync_point = &sync_point_perfmon_sample_post; in etnaviv_gpu_submit()
1432 gpu->event[event[2]].submit = submit; in etnaviv_gpu_submit()
1433 etnaviv_sync_point_queue(gpu, event[2]); in etnaviv_gpu_submit()
1437 mutex_unlock(&gpu->lock); in etnaviv_gpu_submit()
1444 struct etnaviv_gpu *gpu = container_of(work, struct etnaviv_gpu, in sync_point_worker() local
1446 struct etnaviv_event *event = &gpu->event[gpu->sync_point_event]; in sync_point_worker()
1447 u32 addr = gpu_read(gpu, VIVS_FE_DMA_ADDRESS); in sync_point_worker()
1449 event->sync_point(gpu, event); in sync_point_worker()
1451 event_free(gpu, gpu->sync_point_event); in sync_point_worker()
1454 etnaviv_gpu_start_fe(gpu, addr + 2, 2); in sync_point_worker()
1457 static void dump_mmu_fault(struct etnaviv_gpu *gpu) in dump_mmu_fault() argument
1471 if (gpu->sec_mode == ETNA_SEC_NONE) in dump_mmu_fault()
1476 status = gpu_read(gpu, status_reg); in dump_mmu_fault()
1477 dev_err_ratelimited(gpu->dev, "MMU fault status 0x%08x\n", status); in dump_mmu_fault()
1491 if (gpu->sec_mode == ETNA_SEC_NONE) in dump_mmu_fault()
1496 dev_err_ratelimited(gpu->dev, in dump_mmu_fault()
1498 i, reason, gpu_read(gpu, address_reg)); in dump_mmu_fault()
1504 struct etnaviv_gpu *gpu = data; in irq_handler() local
1507 u32 intr = gpu_read(gpu, VIVS_HI_INTR_ACKNOWLEDGE); in irq_handler()
1512 pm_runtime_mark_last_busy(gpu->dev); in irq_handler()
1514 dev_dbg(gpu->dev, "intr 0x%08x\n", intr); in irq_handler()
1517 dev_err(gpu->dev, "AXI bus error\n"); in irq_handler()
1522 dump_mmu_fault(gpu); in irq_handler()
1533 dev_dbg(gpu->dev, "event %u\n", event); in irq_handler()
1535 if (gpu->event[event].sync_point) { in irq_handler()
1536 gpu->sync_point_event = event; in irq_handler()
1537 queue_work(gpu->wq, &gpu->sync_point_work); in irq_handler()
1540 fence = gpu->event[event].fence; in irq_handler()
1544 gpu->event[event].fence = NULL; in irq_handler()
1555 if (fence_after(fence->seqno, gpu->completed_fence)) in irq_handler()
1556 gpu->completed_fence = fence->seqno; in irq_handler()
1559 event_free(gpu, event); in irq_handler()
1568 static int etnaviv_gpu_clk_enable(struct etnaviv_gpu *gpu) in etnaviv_gpu_clk_enable() argument
1572 ret = clk_prepare_enable(gpu->clk_reg); in etnaviv_gpu_clk_enable()
1576 ret = clk_prepare_enable(gpu->clk_bus); in etnaviv_gpu_clk_enable()
1580 ret = clk_prepare_enable(gpu->clk_core); in etnaviv_gpu_clk_enable()
1584 ret = clk_prepare_enable(gpu->clk_shader); in etnaviv_gpu_clk_enable()
1591 clk_disable_unprepare(gpu->clk_core); in etnaviv_gpu_clk_enable()
1593 clk_disable_unprepare(gpu->clk_bus); in etnaviv_gpu_clk_enable()
1595 clk_disable_unprepare(gpu->clk_reg); in etnaviv_gpu_clk_enable()
1600 static int etnaviv_gpu_clk_disable(struct etnaviv_gpu *gpu) in etnaviv_gpu_clk_disable() argument
1602 clk_disable_unprepare(gpu->clk_shader); in etnaviv_gpu_clk_disable()
1603 clk_disable_unprepare(gpu->clk_core); in etnaviv_gpu_clk_disable()
1604 clk_disable_unprepare(gpu->clk_bus); in etnaviv_gpu_clk_disable()
1605 clk_disable_unprepare(gpu->clk_reg); in etnaviv_gpu_clk_disable()
1610 int etnaviv_gpu_wait_idle(struct etnaviv_gpu *gpu, unsigned int timeout_ms) in etnaviv_gpu_wait_idle() argument
1615 u32 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE); in etnaviv_gpu_wait_idle()
1617 if ((idle & gpu->idle_mask) == gpu->idle_mask) in etnaviv_gpu_wait_idle()
1621 dev_warn(gpu->dev, in etnaviv_gpu_wait_idle()
1631 static int etnaviv_gpu_hw_suspend(struct etnaviv_gpu *gpu) in etnaviv_gpu_hw_suspend() argument
1633 if (gpu->initialized && gpu->fe_running) { in etnaviv_gpu_hw_suspend()
1635 mutex_lock(&gpu->lock); in etnaviv_gpu_hw_suspend()
1636 etnaviv_buffer_end(gpu); in etnaviv_gpu_hw_suspend()
1637 mutex_unlock(&gpu->lock); in etnaviv_gpu_hw_suspend()
1644 etnaviv_gpu_wait_idle(gpu, 100); in etnaviv_gpu_hw_suspend()
1646 gpu->fe_running = false; in etnaviv_gpu_hw_suspend()
1649 gpu->exec_state = -1; in etnaviv_gpu_hw_suspend()
1651 return etnaviv_gpu_clk_disable(gpu); in etnaviv_gpu_hw_suspend()
1654 static int etnaviv_gpu_hw_resume(struct etnaviv_gpu *gpu) in etnaviv_gpu_hw_resume() argument
1658 ret = mutex_lock_killable(&gpu->lock); in etnaviv_gpu_hw_resume()
1662 etnaviv_gpu_update_clock(gpu); in etnaviv_gpu_hw_resume()
1663 etnaviv_gpu_hw_init(gpu); in etnaviv_gpu_hw_resume()
1665 mutex_unlock(&gpu->lock); in etnaviv_gpu_hw_resume()
1683 struct etnaviv_gpu *gpu = cdev->devdata; in etnaviv_gpu_cooling_get_cur_state() local
1685 *state = gpu->freq_scale; in etnaviv_gpu_cooling_get_cur_state()
1694 struct etnaviv_gpu *gpu = cdev->devdata; in etnaviv_gpu_cooling_set_cur_state() local
1696 mutex_lock(&gpu->lock); in etnaviv_gpu_cooling_set_cur_state()
1697 gpu->freq_scale = state; in etnaviv_gpu_cooling_set_cur_state()
1698 if (!pm_runtime_suspended(gpu->dev)) in etnaviv_gpu_cooling_set_cur_state()
1699 etnaviv_gpu_update_clock(gpu); in etnaviv_gpu_cooling_set_cur_state()
1700 mutex_unlock(&gpu->lock); in etnaviv_gpu_cooling_set_cur_state()
1716 struct etnaviv_gpu *gpu = dev_get_drvdata(dev); in etnaviv_gpu_bind() local
1720 gpu->cooling = thermal_of_cooling_device_register(dev->of_node, in etnaviv_gpu_bind()
1721 (char *)dev_name(dev), gpu, &cooling_ops); in etnaviv_gpu_bind()
1722 if (IS_ERR(gpu->cooling)) in etnaviv_gpu_bind()
1723 return PTR_ERR(gpu->cooling); in etnaviv_gpu_bind()
1726 gpu->wq = alloc_ordered_workqueue(dev_name(dev), 0); in etnaviv_gpu_bind()
1727 if (!gpu->wq) { in etnaviv_gpu_bind()
1732 ret = etnaviv_sched_init(gpu); in etnaviv_gpu_bind()
1737 ret = pm_runtime_get_sync(gpu->dev); in etnaviv_gpu_bind()
1739 ret = etnaviv_gpu_clk_enable(gpu); in etnaviv_gpu_bind()
1744 gpu->drm = drm; in etnaviv_gpu_bind()
1745 gpu->fence_context = dma_fence_context_alloc(1); in etnaviv_gpu_bind()
1746 xa_init_flags(&gpu->user_fences, XA_FLAGS_ALLOC); in etnaviv_gpu_bind()
1747 spin_lock_init(&gpu->fence_spinlock); in etnaviv_gpu_bind()
1749 INIT_WORK(&gpu->sync_point_work, sync_point_worker); in etnaviv_gpu_bind()
1750 init_waitqueue_head(&gpu->fence_event); in etnaviv_gpu_bind()
1752 priv->gpu[priv->num_gpus++] = gpu; in etnaviv_gpu_bind()
1754 pm_runtime_mark_last_busy(gpu->dev); in etnaviv_gpu_bind()
1755 pm_runtime_put_autosuspend(gpu->dev); in etnaviv_gpu_bind()
1760 etnaviv_sched_fini(gpu); in etnaviv_gpu_bind()
1763 destroy_workqueue(gpu->wq); in etnaviv_gpu_bind()
1767 thermal_cooling_device_unregister(gpu->cooling); in etnaviv_gpu_bind()
1775 struct etnaviv_gpu *gpu = dev_get_drvdata(dev); in etnaviv_gpu_unbind() local
1777 DBG("%s", dev_name(gpu->dev)); in etnaviv_gpu_unbind()
1779 destroy_workqueue(gpu->wq); in etnaviv_gpu_unbind()
1781 etnaviv_sched_fini(gpu); in etnaviv_gpu_unbind()
1784 pm_runtime_get_sync(gpu->dev); in etnaviv_gpu_unbind()
1785 pm_runtime_put_sync_suspend(gpu->dev); in etnaviv_gpu_unbind()
1787 etnaviv_gpu_hw_suspend(gpu); in etnaviv_gpu_unbind()
1790 if (gpu->mmu_context) in etnaviv_gpu_unbind()
1791 etnaviv_iommu_context_put(gpu->mmu_context); in etnaviv_gpu_unbind()
1793 if (gpu->initialized) { in etnaviv_gpu_unbind()
1794 etnaviv_cmdbuf_free(&gpu->buffer); in etnaviv_gpu_unbind()
1795 etnaviv_iommu_global_fini(gpu); in etnaviv_gpu_unbind()
1796 gpu->initialized = false; in etnaviv_gpu_unbind()
1799 gpu->drm = NULL; in etnaviv_gpu_unbind()
1800 xa_destroy(&gpu->user_fences); in etnaviv_gpu_unbind()
1803 thermal_cooling_device_unregister(gpu->cooling); in etnaviv_gpu_unbind()
1804 gpu->cooling = NULL; in etnaviv_gpu_unbind()
1823 struct etnaviv_gpu *gpu; in etnaviv_gpu_platform_probe() local
1826 gpu = devm_kzalloc(dev, sizeof(*gpu), GFP_KERNEL); in etnaviv_gpu_platform_probe()
1827 if (!gpu) in etnaviv_gpu_platform_probe()
1830 gpu->dev = &pdev->dev; in etnaviv_gpu_platform_probe()
1831 mutex_init(&gpu->lock); in etnaviv_gpu_platform_probe()
1832 mutex_init(&gpu->sched_lock); in etnaviv_gpu_platform_probe()
1835 gpu->mmio = devm_platform_ioremap_resource(pdev, 0); in etnaviv_gpu_platform_probe()
1836 if (IS_ERR(gpu->mmio)) in etnaviv_gpu_platform_probe()
1837 return PTR_ERR(gpu->mmio); in etnaviv_gpu_platform_probe()
1840 gpu->irq = platform_get_irq(pdev, 0); in etnaviv_gpu_platform_probe()
1841 if (gpu->irq < 0) in etnaviv_gpu_platform_probe()
1842 return gpu->irq; in etnaviv_gpu_platform_probe()
1844 err = devm_request_irq(&pdev->dev, gpu->irq, irq_handler, 0, in etnaviv_gpu_platform_probe()
1845 dev_name(gpu->dev), gpu); in etnaviv_gpu_platform_probe()
1847 dev_err(dev, "failed to request IRQ%u: %d\n", gpu->irq, err); in etnaviv_gpu_platform_probe()
1852 gpu->clk_reg = devm_clk_get_optional(&pdev->dev, "reg"); in etnaviv_gpu_platform_probe()
1853 DBG("clk_reg: %p", gpu->clk_reg); in etnaviv_gpu_platform_probe()
1854 if (IS_ERR(gpu->clk_reg)) in etnaviv_gpu_platform_probe()
1855 return PTR_ERR(gpu->clk_reg); in etnaviv_gpu_platform_probe()
1857 gpu->clk_bus = devm_clk_get_optional(&pdev->dev, "bus"); in etnaviv_gpu_platform_probe()
1858 DBG("clk_bus: %p", gpu->clk_bus); in etnaviv_gpu_platform_probe()
1859 if (IS_ERR(gpu->clk_bus)) in etnaviv_gpu_platform_probe()
1860 return PTR_ERR(gpu->clk_bus); in etnaviv_gpu_platform_probe()
1862 gpu->clk_core = devm_clk_get(&pdev->dev, "core"); in etnaviv_gpu_platform_probe()
1863 DBG("clk_core: %p", gpu->clk_core); in etnaviv_gpu_platform_probe()
1864 if (IS_ERR(gpu->clk_core)) in etnaviv_gpu_platform_probe()
1865 return PTR_ERR(gpu->clk_core); in etnaviv_gpu_platform_probe()
1866 gpu->base_rate_core = clk_get_rate(gpu->clk_core); in etnaviv_gpu_platform_probe()
1868 gpu->clk_shader = devm_clk_get_optional(&pdev->dev, "shader"); in etnaviv_gpu_platform_probe()
1869 DBG("clk_shader: %p", gpu->clk_shader); in etnaviv_gpu_platform_probe()
1870 if (IS_ERR(gpu->clk_shader)) in etnaviv_gpu_platform_probe()
1871 return PTR_ERR(gpu->clk_shader); in etnaviv_gpu_platform_probe()
1872 gpu->base_rate_shader = clk_get_rate(gpu->clk_shader); in etnaviv_gpu_platform_probe()
1875 dev_set_drvdata(dev, gpu); in etnaviv_gpu_platform_probe()
1882 pm_runtime_use_autosuspend(gpu->dev); in etnaviv_gpu_platform_probe()
1883 pm_runtime_set_autosuspend_delay(gpu->dev, 200); in etnaviv_gpu_platform_probe()
1884 pm_runtime_enable(gpu->dev); in etnaviv_gpu_platform_probe()
1904 struct etnaviv_gpu *gpu = dev_get_drvdata(dev); in etnaviv_gpu_rpm_suspend() local
1908 if (atomic_read(&gpu->sched.hw_rq_count)) in etnaviv_gpu_rpm_suspend()
1912 mask = gpu->idle_mask & ~(VIVS_HI_IDLE_STATE_FE | in etnaviv_gpu_rpm_suspend()
1914 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE) & mask; in etnaviv_gpu_rpm_suspend()
1921 return etnaviv_gpu_hw_suspend(gpu); in etnaviv_gpu_rpm_suspend()
1926 struct etnaviv_gpu *gpu = dev_get_drvdata(dev); in etnaviv_gpu_rpm_resume() local
1929 ret = etnaviv_gpu_clk_enable(gpu); in etnaviv_gpu_rpm_resume()
1934 if (gpu->drm && gpu->initialized) { in etnaviv_gpu_rpm_resume()
1935 ret = etnaviv_gpu_hw_resume(gpu); in etnaviv_gpu_rpm_resume()
1937 etnaviv_gpu_clk_disable(gpu); in etnaviv_gpu_rpm_resume()