Lines Matching refs:reg_values
266 const unsigned int *reg_values; member
411 static const unsigned int reg_values[] = { variable
474 .reg_values = reg_values,
486 .reg_values = reg_values,
496 .reg_values = reg_values,
507 .reg_values = exynos5433_reg_values,
518 .reg_values = exynos5422_reg_values,
545 u32 reset_val = dsi->driver_data->reg_values[RESET_TYPE]; in exynos_dsi_reset()
628 writel(driver_data->reg_values[PLL_TIMER], in exynos_dsi_set_pll()
707 const unsigned int *reg_values = driver_data->reg_values; in exynos_dsi_set_phy_ctrl() local
714 reg = reg_values[PHYCTRL_ULPS_EXIT] | reg_values[PHYCTRL_VREG_LP] | in exynos_dsi_set_phy_ctrl()
715 reg_values[PHYCTRL_SLEW_UP]; in exynos_dsi_set_phy_ctrl()
723 reg = reg_values[PHYTIMING_LPX] | reg_values[PHYTIMING_HS_EXIT]; in exynos_dsi_set_phy_ctrl()
739 reg = reg_values[PHYTIMING_CLK_PREPARE] | in exynos_dsi_set_phy_ctrl()
740 reg_values[PHYTIMING_CLK_ZERO] | in exynos_dsi_set_phy_ctrl()
741 reg_values[PHYTIMING_CLK_POST] | in exynos_dsi_set_phy_ctrl()
742 reg_values[PHYTIMING_CLK_TRAIL]; in exynos_dsi_set_phy_ctrl()
755 reg = reg_values[PHYTIMING_HS_PREPARE] | reg_values[PHYTIMING_HS_ZERO] | in exynos_dsi_set_phy_ctrl()
756 reg_values[PHYTIMING_HS_TRAIL]; in exynos_dsi_set_phy_ctrl()
887 reg |= DSIM_STOP_STATE_CNT(driver_data->reg_values[STOP_STATE_CNT]); in exynos_dsi_init_link()
1333 if (driver_data->reg_values[RESET_TYPE] == DSIM_FUNCRST) in exynos_dsi_init()