Lines Matching refs:REG_READ
36 REG_READ(vga_reg); in cdv_disable_vga()
51 if (REG_READ(SDVOB) & SDVO_DETECTED) { in cdv_output_init()
53 if (REG_READ(DP_B) & DP_DETECTED) in cdv_output_init()
57 if (REG_READ(SDVOC) & SDVO_DETECTED) { in cdv_output_init()
59 if (REG_READ(DP_C) & DP_DETECTED) in cdv_output_init()
71 return REG_READ(BLC_PWM_CTL2) & PWM_LEGACY_MODE; in cdv_backlight_combination_mode()
76 u32 max = REG_READ(BLC_PWM_CTL); in cdv_get_max_backlight()
94 u32 val = REG_READ(BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK; in cdv_get_brightness()
124 blc_pwm_ctl = REG_READ(BLC_PWM_CTL) & ~BACKLIGHT_DUTY_CYCLE_MASK; in cdv_set_brightness()
240 regs->cdv.saveDSPCLK_GATE_D = REG_READ(DSPCLK_GATE_D); in cdv_save_display_registers()
241 regs->cdv.saveRAMCLK_GATE_D = REG_READ(RAMCLK_GATE_D); in cdv_save_display_registers()
243 regs->cdv.saveDSPARB = REG_READ(DSPARB); in cdv_save_display_registers()
244 regs->cdv.saveDSPFW[0] = REG_READ(DSPFW1); in cdv_save_display_registers()
245 regs->cdv.saveDSPFW[1] = REG_READ(DSPFW2); in cdv_save_display_registers()
246 regs->cdv.saveDSPFW[2] = REG_READ(DSPFW3); in cdv_save_display_registers()
247 regs->cdv.saveDSPFW[3] = REG_READ(DSPFW4); in cdv_save_display_registers()
248 regs->cdv.saveDSPFW[4] = REG_READ(DSPFW5); in cdv_save_display_registers()
249 regs->cdv.saveDSPFW[5] = REG_READ(DSPFW6); in cdv_save_display_registers()
251 regs->cdv.saveADPA = REG_READ(ADPA); in cdv_save_display_registers()
253 regs->cdv.savePP_CONTROL = REG_READ(PP_CONTROL); in cdv_save_display_registers()
254 regs->cdv.savePFIT_PGM_RATIOS = REG_READ(PFIT_PGM_RATIOS); in cdv_save_display_registers()
255 regs->saveBLC_PWM_CTL = REG_READ(BLC_PWM_CTL); in cdv_save_display_registers()
256 regs->saveBLC_PWM_CTL2 = REG_READ(BLC_PWM_CTL2); in cdv_save_display_registers()
257 regs->cdv.saveLVDS = REG_READ(LVDS); in cdv_save_display_registers()
259 regs->cdv.savePFIT_CONTROL = REG_READ(PFIT_CONTROL); in cdv_save_display_registers()
261 regs->cdv.savePP_ON_DELAYS = REG_READ(PP_ON_DELAYS); in cdv_save_display_registers()
262 regs->cdv.savePP_OFF_DELAYS = REG_READ(PP_OFF_DELAYS); in cdv_save_display_registers()
263 regs->cdv.savePP_CYCLE = REG_READ(PP_CYCLE); in cdv_save_display_registers()
265 regs->cdv.saveVGACNTRL = REG_READ(VGACNTRL); in cdv_save_display_registers()
267 regs->cdv.saveIER = REG_READ(PSB_INT_ENABLE_R); in cdv_save_display_registers()
268 regs->cdv.saveIMR = REG_READ(PSB_INT_MASK_R); in cdv_save_display_registers()
304 temp = REG_READ(DPLL_A); in cdv_restore_display_registers()
307 REG_READ(DPLL_A); in cdv_restore_display_registers()
310 temp = REG_READ(DPLL_B); in cdv_restore_display_registers()
313 REG_READ(DPLL_B); in cdv_restore_display_registers()
419 REG_WRITE(PORT_HOTPLUG_STAT, REG_READ(PORT_HOTPLUG_STAT)); in cdv_hotplug_event()
426 u32 hotplug = REG_READ(PORT_HOTPLUG_EN); in cdv_hotplug_enable()
432 REG_WRITE(PORT_HOTPLUG_STAT, REG_READ(PORT_HOTPLUG_STAT)); in cdv_hotplug_enable()