Lines Matching refs:REG_READ
134 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000); in cdv_sb_read()
146 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000); in cdv_sb_read()
152 *val = REG_READ(SB_DATA); in cdv_sb_read()
169 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000); in cdv_sb_write()
182 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000); in cdv_sb_write()
203 REG_READ(DPIO_CFG); in cdv_sb_reset()
472 if (REG_READ(FW_BLC_SELF) & FW_BLC_SELF_EN) { in cdv_disable_sr()
475 REG_WRITE(FW_BLC_SELF, (REG_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN)); in cdv_disable_sr()
476 REG_READ(FW_BLC_SELF); in cdv_disable_sr()
484 REG_READ(OV_OVADD); in cdv_disable_sr()
500 fw = REG_READ(DSPFW1); in cdv_update_wm()
507 fw = REG_READ(DSPFW2); in cdv_update_wm()
536 REG_READ(FW_BLC_SELF); in cdv_update_wm()
563 pfit_control = REG_READ(PFIT_CONTROL); in cdv_intel_panel_fitter_pipe()
684 pipeconf = REG_READ(map->conf); in cdv_intel_crtc_mode_set()
704 if ((REG_READ(LVDS) & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP) in cdv_intel_crtc_mode_set()
723 REG_READ(map->dpll); in cdv_intel_crtc_mode_set()
735 u32 lvds = REG_READ(LVDS); in cdv_intel_crtc_mode_set()
755 REG_READ(LVDS); in cdv_intel_crtc_mode_set()
768 (REG_READ(map->dpll) & ~DPLL_LOCK) | DPLL_VCO_ENABLE); in cdv_intel_crtc_mode_set()
769 REG_READ(map->dpll); in cdv_intel_crtc_mode_set()
773 if (!(REG_READ(map->dpll) & DPLL_LOCK)) { in cdv_intel_crtc_mode_set()
804 REG_READ(map->conf); in cdv_intel_crtc_mode_set()
849 dpll = REG_READ(map->dpll); in cdv_intel_crtc_clock_get()
851 fp = REG_READ(map->fp0); in cdv_intel_crtc_clock_get()
853 fp = REG_READ(map->fp1); in cdv_intel_crtc_clock_get()
854 is_lvds = (pipe == 1) && (REG_READ(LVDS) & LVDS_PORT_EN); in cdv_intel_crtc_clock_get()
929 htot = REG_READ(map->htotal); in cdv_intel_crtc_mode_get()
930 hsync = REG_READ(map->hsync); in cdv_intel_crtc_mode_get()
931 vtot = REG_READ(map->vtotal); in cdv_intel_crtc_mode_get()
932 vsync = REG_READ(map->vsync); in cdv_intel_crtc_mode_get()