Lines Matching refs:dpll
245 temp = REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_dpms()
247 REG_WRITE_WITH_AUX(map->dpll, temp, i); in oaktrail_crtc_dpms()
248 REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_dpms()
251 REG_WRITE_WITH_AUX(map->dpll, in oaktrail_crtc_dpms()
253 REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_dpms()
256 REG_WRITE_WITH_AUX(map->dpll, in oaktrail_crtc_dpms()
258 REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_dpms()
317 temp = REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_dpms()
319 REG_WRITE_WITH_AUX(map->dpll, in oaktrail_crtc_dpms()
321 REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_dpms()
373 u32 dpll = 0, fp = 0, dspcntr, pipeconf; in oaktrail_crtc_mode_set() local
503 dpll = 0; /*BIT16 = 0 for 100MHz reference */ in oaktrail_crtc_mode_set()
527 dpll |= DPLL_VGA_MODE_DIS; in oaktrail_crtc_mode_set()
530 dpll |= DPLL_VCO_ENABLE; in oaktrail_crtc_mode_set()
533 dpll |= DPLLA_MODE_LVDS; in oaktrail_crtc_mode_set()
535 dpll |= DPLLB_MODE_DAC_SERIAL; in oaktrail_crtc_mode_set()
541 dpll |= DPLL_DVO_HIGH_SPEED; in oaktrail_crtc_mode_set()
542 dpll |= in oaktrail_crtc_mode_set()
550 dpll |= clock.p1 << 16; // dpll |= (1 << (clock.p1 - 1)) << 16; in oaktrail_crtc_mode_set()
552 dpll |= (1 << (clock.p1 - 2)) << 17; in oaktrail_crtc_mode_set()
554 dpll |= DPLL_VCO_ENABLE; in oaktrail_crtc_mode_set()
556 if (dpll & DPLL_VCO_ENABLE) { in oaktrail_crtc_mode_set()
559 REG_WRITE_WITH_AUX(map->dpll, dpll & ~DPLL_VCO_ENABLE, i); in oaktrail_crtc_mode_set()
560 REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_mode_set()
568 REG_WRITE_WITH_AUX(map->dpll, dpll, i); in oaktrail_crtc_mode_set()
569 REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_mode_set()
574 REG_WRITE_WITH_AUX(map->dpll, dpll, i); in oaktrail_crtc_mode_set()
575 REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_mode_set()