Lines Matching refs:i9xx_plane
110 enum i9xx_plane_id i9xx_plane) in i9xx_plane_has_fbc() argument
116 return i9xx_plane == PLANE_A; /* tied to pipe A */ in i9xx_plane_has_fbc()
118 return i9xx_plane == PLANE_A || i9xx_plane == PLANE_B || in i9xx_plane_has_fbc()
119 i9xx_plane == PLANE_C; in i9xx_plane_has_fbc()
121 return i9xx_plane == PLANE_A || i9xx_plane == PLANE_B; in i9xx_plane_has_fbc()
123 return i9xx_plane == PLANE_A; in i9xx_plane_has_fbc()
127 enum i9xx_plane_id i9xx_plane) in i9xx_plane_fbc() argument
129 if (i9xx_plane_has_fbc(dev_priv, i9xx_plane)) in i9xx_plane_fbc()
138 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; in i9xx_plane_has_windowing() local
141 return i9xx_plane == PLANE_B; in i9xx_plane_has_windowing()
145 return i9xx_plane == PLANE_C; in i9xx_plane_has_windowing()
147 return i9xx_plane == PLANE_B || in i9xx_plane_has_windowing()
148 i9xx_plane == PLANE_C; in i9xx_plane_has_windowing()
422 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; in i9xx_plane_update_noarm() local
424 intel_de_write_fw(dev_priv, DSPSTRIDE(i9xx_plane), in i9xx_plane_update_noarm()
438 intel_de_write_fw(dev_priv, DSPPOS(i9xx_plane), in i9xx_plane_update_noarm()
440 intel_de_write_fw(dev_priv, DSPSIZE(i9xx_plane), in i9xx_plane_update_noarm()
450 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; in i9xx_plane_update_arm() local
464 if (IS_CHERRYVIEW(dev_priv) && i9xx_plane == PLANE_B) { in i9xx_plane_update_arm()
470 intel_de_write_fw(dev_priv, PRIMPOS(i9xx_plane), in i9xx_plane_update_arm()
472 intel_de_write_fw(dev_priv, PRIMSIZE(i9xx_plane), in i9xx_plane_update_arm()
474 intel_de_write_fw(dev_priv, PRIMCNSTALPHA(i9xx_plane), 0); in i9xx_plane_update_arm()
478 intel_de_write_fw(dev_priv, DSPOFFSET(i9xx_plane), in i9xx_plane_update_arm()
481 intel_de_write_fw(dev_priv, DSPLINOFF(i9xx_plane), in i9xx_plane_update_arm()
483 intel_de_write_fw(dev_priv, DSPTILEOFF(i9xx_plane), in i9xx_plane_update_arm()
492 intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane), dspcntr); in i9xx_plane_update_arm()
495 intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane), in i9xx_plane_update_arm()
498 intel_de_write_fw(dev_priv, DSPADDR(i9xx_plane), in i9xx_plane_update_arm()
520 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; in i9xx_plane_disable_arm() local
535 intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane), dspcntr); in i9xx_plane_disable_arm()
538 intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane), 0); in i9xx_plane_disable_arm()
540 intel_de_write_fw(dev_priv, DSPADDR(i9xx_plane), 0); in i9xx_plane_disable_arm()
552 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; in g4x_primary_async_flip() local
557 intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane), dspcntr); in g4x_primary_async_flip()
559 intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane), in g4x_primary_async_flip()
571 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; in vlv_primary_async_flip() local
573 intel_de_write_fw(dev_priv, DSPADDR_VLV(i9xx_plane), in vlv_primary_async_flip()
605 ilk_enable_display_irq(i915, DE_PLANE_FLIP_DONE_IVB(plane->i9xx_plane)); in ivb_primary_enable_flip_done()
615 ilk_disable_display_irq(i915, DE_PLANE_FLIP_DONE_IVB(plane->i9xx_plane)); in ivb_primary_disable_flip_done()
625 ilk_enable_display_irq(i915, DE_PLANE_FLIP_DONE(plane->i9xx_plane)); in ilk_primary_enable_flip_done()
635 ilk_disable_display_irq(i915, DE_PLANE_FLIP_DONE(plane->i9xx_plane)); in ilk_primary_disable_flip_done()
666 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; in i9xx_plane_get_hw_state() local
681 val = intel_de_read(dev_priv, DSPCNTR(i9xx_plane)); in i9xx_plane_get_hw_state()
750 if (plane->i9xx_plane == PLANE_C) in i9xx_plane_max_stride()
797 plane->i9xx_plane = (enum i9xx_plane_id) !pipe; in intel_primary_plane_create()
799 plane->i9xx_plane = (enum i9xx_plane_id) pipe; in intel_primary_plane_create()
803 intel_fbc_add_plane(i9xx_plane_fbc(dev_priv, plane->i9xx_plane), plane); in intel_primary_plane_create()
905 plane_name(plane->i9xx_plane)); in intel_primary_plane_create()
981 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; in i9xx_get_initial_plane_config() local
1004 val = intel_de_read(dev_priv, DSPCNTR(i9xx_plane)); in i9xx_get_initial_plane_config()
1025 offset = intel_de_read(dev_priv, DSPOFFSET(i9xx_plane)); in i9xx_get_initial_plane_config()
1026 base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)) & DISP_ADDR_MASK; in i9xx_get_initial_plane_config()
1030 DSPTILEOFF(i9xx_plane)); in i9xx_get_initial_plane_config()
1033 DSPLINOFF(i9xx_plane)); in i9xx_get_initial_plane_config()
1034 base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)) & DISP_ADDR_MASK; in i9xx_get_initial_plane_config()
1036 base = intel_de_read(dev_priv, DSPADDR(i9xx_plane)); in i9xx_get_initial_plane_config()
1044 val = intel_de_read(dev_priv, DSPSTRIDE(i9xx_plane)); in i9xx_get_initial_plane_config()