Lines Matching refs:cdclk_config
72 struct intel_cdclk_config *cdclk_config);
74 const struct intel_cdclk_config *cdclk_config,
81 struct intel_cdclk_config *cdclk_config) in intel_cdclk_get_cdclk() argument
83 dev_priv->display.funcs.cdclk->get_cdclk(dev_priv, cdclk_config); in intel_cdclk_get_cdclk()
87 const struct intel_cdclk_config *cdclk_config, in intel_cdclk_set_cdclk() argument
90 dev_priv->display.funcs.cdclk->set_cdclk(dev_priv, cdclk_config, pipe); in intel_cdclk_set_cdclk()
94 struct intel_cdclk_state *cdclk_config) in intel_cdclk_modeset_calc_cdclk() argument
96 return dev_priv->display.funcs.cdclk->modeset_calc_cdclk(cdclk_config); in intel_cdclk_modeset_calc_cdclk()
106 struct intel_cdclk_config *cdclk_config) in fixed_133mhz_get_cdclk() argument
108 cdclk_config->cdclk = 133333; in fixed_133mhz_get_cdclk()
112 struct intel_cdclk_config *cdclk_config) in fixed_200mhz_get_cdclk() argument
114 cdclk_config->cdclk = 200000; in fixed_200mhz_get_cdclk()
118 struct intel_cdclk_config *cdclk_config) in fixed_266mhz_get_cdclk() argument
120 cdclk_config->cdclk = 266667; in fixed_266mhz_get_cdclk()
124 struct intel_cdclk_config *cdclk_config) in fixed_333mhz_get_cdclk() argument
126 cdclk_config->cdclk = 333333; in fixed_333mhz_get_cdclk()
130 struct intel_cdclk_config *cdclk_config) in fixed_400mhz_get_cdclk() argument
132 cdclk_config->cdclk = 400000; in fixed_400mhz_get_cdclk()
136 struct intel_cdclk_config *cdclk_config) in fixed_450mhz_get_cdclk() argument
138 cdclk_config->cdclk = 450000; in fixed_450mhz_get_cdclk()
142 struct intel_cdclk_config *cdclk_config) in i85x_get_cdclk() argument
153 cdclk_config->cdclk = 133333; in i85x_get_cdclk()
167 cdclk_config->cdclk = 200000; in i85x_get_cdclk()
170 cdclk_config->cdclk = 250000; in i85x_get_cdclk()
173 cdclk_config->cdclk = 133333; in i85x_get_cdclk()
178 cdclk_config->cdclk = 266667; in i85x_get_cdclk()
184 struct intel_cdclk_config *cdclk_config) in i915gm_get_cdclk() argument
192 cdclk_config->cdclk = 133333; in i915gm_get_cdclk()
198 cdclk_config->cdclk = 333333; in i915gm_get_cdclk()
202 cdclk_config->cdclk = 190000; in i915gm_get_cdclk()
208 struct intel_cdclk_config *cdclk_config) in i945gm_get_cdclk() argument
216 cdclk_config->cdclk = 133333; in i945gm_get_cdclk()
222 cdclk_config->cdclk = 320000; in i945gm_get_cdclk()
226 cdclk_config->cdclk = 200000; in i945gm_get_cdclk()
302 struct intel_cdclk_config *cdclk_config) in g33_get_cdclk() argument
313 cdclk_config->vco = intel_hpll_vco(dev_priv); in g33_get_cdclk()
322 switch (cdclk_config->vco) { in g33_get_cdclk()
339 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, in g33_get_cdclk()
346 cdclk_config->vco, tmp); in g33_get_cdclk()
347 cdclk_config->cdclk = 190476; in g33_get_cdclk()
351 struct intel_cdclk_config *cdclk_config) in pnv_get_cdclk() argument
360 cdclk_config->cdclk = 266667; in pnv_get_cdclk()
363 cdclk_config->cdclk = 333333; in pnv_get_cdclk()
366 cdclk_config->cdclk = 444444; in pnv_get_cdclk()
369 cdclk_config->cdclk = 200000; in pnv_get_cdclk()
376 cdclk_config->cdclk = 133333; in pnv_get_cdclk()
379 cdclk_config->cdclk = 166667; in pnv_get_cdclk()
385 struct intel_cdclk_config *cdclk_config) in i965gm_get_cdclk() argument
395 cdclk_config->vco = intel_hpll_vco(dev_priv); in i965gm_get_cdclk()
404 switch (cdclk_config->vco) { in i965gm_get_cdclk()
418 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, in i965gm_get_cdclk()
425 cdclk_config->vco, tmp); in i965gm_get_cdclk()
426 cdclk_config->cdclk = 200000; in i965gm_get_cdclk()
430 struct intel_cdclk_config *cdclk_config) in gm45_get_cdclk() argument
436 cdclk_config->vco = intel_hpll_vco(dev_priv); in gm45_get_cdclk()
442 switch (cdclk_config->vco) { in gm45_get_cdclk()
446 cdclk_config->cdclk = cdclk_sel ? 333333 : 222222; in gm45_get_cdclk()
449 cdclk_config->cdclk = cdclk_sel ? 320000 : 228571; in gm45_get_cdclk()
454 cdclk_config->vco, tmp); in gm45_get_cdclk()
455 cdclk_config->cdclk = 222222; in gm45_get_cdclk()
461 struct intel_cdclk_config *cdclk_config) in hsw_get_cdclk() argument
467 cdclk_config->cdclk = 800000; in hsw_get_cdclk()
469 cdclk_config->cdclk = 450000; in hsw_get_cdclk()
471 cdclk_config->cdclk = 450000; in hsw_get_cdclk()
473 cdclk_config->cdclk = 337500; in hsw_get_cdclk()
475 cdclk_config->cdclk = 540000; in hsw_get_cdclk()
518 struct intel_cdclk_config *cdclk_config) in vlv_get_cdclk() argument
525 cdclk_config->vco = vlv_get_hpll_vco(dev_priv); in vlv_get_cdclk()
526 cdclk_config->cdclk = vlv_get_cck_clock(dev_priv, "cdclk", in vlv_get_cdclk()
528 cdclk_config->vco); in vlv_get_cdclk()
536 cdclk_config->voltage_level = (val & DSPFREQGUAR_MASK) >> in vlv_get_cdclk()
539 cdclk_config->voltage_level = (val & DSPFREQGUAR_MASK_CHV) >> in vlv_get_cdclk()
581 const struct intel_cdclk_config *cdclk_config, in vlv_set_cdclk() argument
584 int cdclk = cdclk_config->cdclk; in vlv_set_cdclk()
585 u32 val, cmd = cdclk_config->voltage_level; in vlv_set_cdclk()
670 const struct intel_cdclk_config *cdclk_config, in chv_set_cdclk() argument
673 int cdclk = cdclk_config->cdclk; in chv_set_cdclk()
674 u32 val, cmd = cdclk_config->voltage_level; in chv_set_cdclk()
745 struct intel_cdclk_config *cdclk_config) in bdw_get_cdclk() argument
751 cdclk_config->cdclk = 800000; in bdw_get_cdclk()
753 cdclk_config->cdclk = 450000; in bdw_get_cdclk()
755 cdclk_config->cdclk = 450000; in bdw_get_cdclk()
757 cdclk_config->cdclk = 540000; in bdw_get_cdclk()
759 cdclk_config->cdclk = 337500; in bdw_get_cdclk()
761 cdclk_config->cdclk = 675000; in bdw_get_cdclk()
767 cdclk_config->voltage_level = in bdw_get_cdclk()
768 bdw_calc_voltage_level(cdclk_config->cdclk); in bdw_get_cdclk()
789 const struct intel_cdclk_config *cdclk_config, in bdw_set_cdclk() argument
792 int cdclk = cdclk_config->cdclk; in bdw_set_cdclk()
833 cdclk_config->voltage_level); in bdw_set_cdclk()
877 struct intel_cdclk_config *cdclk_config) in skl_dpll0_update() argument
881 cdclk_config->ref = 24000; in skl_dpll0_update()
882 cdclk_config->vco = 0; in skl_dpll0_update()
905 cdclk_config->vco = 8100000; in skl_dpll0_update()
909 cdclk_config->vco = 8640000; in skl_dpll0_update()
918 struct intel_cdclk_config *cdclk_config) in skl_get_cdclk() argument
922 skl_dpll0_update(dev_priv, cdclk_config); in skl_get_cdclk()
924 cdclk_config->cdclk = cdclk_config->bypass = cdclk_config->ref; in skl_get_cdclk()
926 if (cdclk_config->vco == 0) in skl_get_cdclk()
931 if (cdclk_config->vco == 8640000) { in skl_get_cdclk()
934 cdclk_config->cdclk = 432000; in skl_get_cdclk()
937 cdclk_config->cdclk = 308571; in skl_get_cdclk()
940 cdclk_config->cdclk = 540000; in skl_get_cdclk()
943 cdclk_config->cdclk = 617143; in skl_get_cdclk()
952 cdclk_config->cdclk = 450000; in skl_get_cdclk()
955 cdclk_config->cdclk = 337500; in skl_get_cdclk()
958 cdclk_config->cdclk = 540000; in skl_get_cdclk()
961 cdclk_config->cdclk = 675000; in skl_get_cdclk()
974 cdclk_config->voltage_level = in skl_get_cdclk()
975 skl_calc_voltage_level(cdclk_config->cdclk); in skl_get_cdclk()
1071 const struct intel_cdclk_config *cdclk_config, in skl_set_cdclk() argument
1074 int cdclk = cdclk_config->cdclk; in skl_set_cdclk()
1075 int vco = cdclk_config->vco; in skl_set_cdclk()
1137 cdclk_config->voltage_level); in skl_set_cdclk()
1186 struct intel_cdclk_config cdclk_config; in skl_cdclk_init_hw() local
1202 cdclk_config = dev_priv->display.cdclk.hw; in skl_cdclk_init_hw()
1204 cdclk_config.vco = dev_priv->skl_preferred_vco_freq; in skl_cdclk_init_hw()
1205 if (cdclk_config.vco == 0) in skl_cdclk_init_hw()
1206 cdclk_config.vco = 8100000; in skl_cdclk_init_hw()
1207 cdclk_config.cdclk = skl_calc_cdclk(0, cdclk_config.vco); in skl_cdclk_init_hw()
1208 cdclk_config.voltage_level = skl_calc_voltage_level(cdclk_config.cdclk); in skl_cdclk_init_hw()
1210 skl_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE); in skl_cdclk_init_hw()
1215 struct intel_cdclk_config cdclk_config = dev_priv->display.cdclk.hw; in skl_cdclk_uninit_hw() local
1217 cdclk_config.cdclk = cdclk_config.bypass; in skl_cdclk_uninit_hw()
1218 cdclk_config.vco = 0; in skl_cdclk_uninit_hw()
1219 cdclk_config.voltage_level = skl_calc_voltage_level(cdclk_config.cdclk); in skl_cdclk_uninit_hw()
1221 skl_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE); in skl_cdclk_uninit_hw()
1433 struct intel_cdclk_config *cdclk_config) in icl_readout_refclk() argument
1442 cdclk_config->ref = 24000; in icl_readout_refclk()
1445 cdclk_config->ref = 19200; in icl_readout_refclk()
1448 cdclk_config->ref = 38400; in icl_readout_refclk()
1454 struct intel_cdclk_config *cdclk_config) in bxt_de_pll_readout() argument
1459 cdclk_config->ref = 38400; in bxt_de_pll_readout()
1461 icl_readout_refclk(dev_priv, cdclk_config); in bxt_de_pll_readout()
1463 cdclk_config->ref = 19200; in bxt_de_pll_readout()
1472 cdclk_config->vco = 0; in bxt_de_pll_readout()
1485 cdclk_config->vco = ratio * cdclk_config->ref; in bxt_de_pll_readout()
1489 struct intel_cdclk_config *cdclk_config) in bxt_get_cdclk() argument
1495 bxt_de_pll_readout(dev_priv, cdclk_config); in bxt_get_cdclk()
1498 cdclk_config->bypass = cdclk_config->ref / 2; in bxt_get_cdclk()
1500 cdclk_config->bypass = 50000; in bxt_get_cdclk()
1502 cdclk_config->bypass = cdclk_config->ref; in bxt_get_cdclk()
1504 if (cdclk_config->vco == 0) { in bxt_get_cdclk()
1505 cdclk_config->cdclk = cdclk_config->bypass; in bxt_get_cdclk()
1539 cdclk_config->cdclk = DIV_ROUND_CLOSEST(hweight16(waveform) * in bxt_get_cdclk()
1540 cdclk_config->vco, size * div); in bxt_get_cdclk()
1542 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, div); in bxt_get_cdclk()
1550 cdclk_config->voltage_level = in bxt_get_cdclk()
1551 intel_cdclk_calc_voltage_level(dev_priv, cdclk_config->cdclk); in bxt_get_cdclk()
1805 const struct intel_cdclk_config *cdclk_config, in _bxt_set_cdclk() argument
1808 int cdclk = cdclk_config->cdclk; in _bxt_set_cdclk()
1809 int vco = cdclk_config->vco; in _bxt_set_cdclk()
1851 const struct intel_cdclk_config *cdclk_config, in bxt_set_cdclk() argument
1855 int cdclk = cdclk_config->cdclk; in bxt_set_cdclk()
1888 cdclk_config, &mid_cdclk_config)) { in bxt_set_cdclk()
1890 _bxt_set_cdclk(dev_priv, cdclk_config, pipe); in bxt_set_cdclk()
1892 _bxt_set_cdclk(dev_priv, cdclk_config, pipe); in bxt_set_cdclk()
1902 cdclk_config->voltage_level); in bxt_set_cdclk()
1912 cdclk_config->voltage_level, in bxt_set_cdclk()
1929 dev_priv->display.cdclk.hw.voltage_level = cdclk_config->voltage_level; in bxt_set_cdclk()
2003 struct intel_cdclk_config cdclk_config; in bxt_cdclk_init_hw() local
2011 cdclk_config = dev_priv->display.cdclk.hw; in bxt_cdclk_init_hw()
2018 cdclk_config.cdclk = bxt_calc_cdclk(dev_priv, 0); in bxt_cdclk_init_hw()
2019 cdclk_config.vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk_config.cdclk); in bxt_cdclk_init_hw()
2020 cdclk_config.voltage_level = in bxt_cdclk_init_hw()
2021 intel_cdclk_calc_voltage_level(dev_priv, cdclk_config.cdclk); in bxt_cdclk_init_hw()
2023 bxt_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE); in bxt_cdclk_init_hw()
2028 struct intel_cdclk_config cdclk_config = dev_priv->display.cdclk.hw; in bxt_cdclk_uninit_hw() local
2030 cdclk_config.cdclk = cdclk_config.bypass; in bxt_cdclk_uninit_hw()
2031 cdclk_config.vco = 0; in bxt_cdclk_uninit_hw()
2032 cdclk_config.voltage_level = in bxt_cdclk_uninit_hw()
2033 intel_cdclk_calc_voltage_level(dev_priv, cdclk_config.cdclk); in bxt_cdclk_uninit_hw()
2035 bxt_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE); in bxt_cdclk_uninit_hw()
2201 const struct intel_cdclk_config *cdclk_config, in intel_cdclk_dump_config() argument
2205 context, cdclk_config->cdclk, cdclk_config->vco, in intel_cdclk_dump_config()
2206 cdclk_config->ref, cdclk_config->bypass, in intel_cdclk_dump_config()
2207 cdclk_config->voltage_level); in intel_cdclk_dump_config()
2220 const struct intel_cdclk_config *cdclk_config, in intel_set_cdclk() argument
2225 if (!intel_cdclk_changed(&dev_priv->display.cdclk.hw, cdclk_config)) in intel_set_cdclk()
2231 intel_cdclk_dump_config(dev_priv, cdclk_config, "Changing CDCLK to"); in intel_set_cdclk()
2254 intel_cdclk_set_cdclk(dev_priv, cdclk_config, pipe); in intel_set_cdclk()
2272 intel_cdclk_changed(&dev_priv->display.cdclk.hw, cdclk_config), in intel_set_cdclk()
2275 intel_cdclk_dump_config(dev_priv, cdclk_config, "[sw state]"); in intel_set_cdclk()