Lines Matching refs:dev_priv
80 void intel_cdclk_get_cdclk(struct drm_i915_private *dev_priv, in intel_cdclk_get_cdclk() argument
83 dev_priv->display.funcs.cdclk->get_cdclk(dev_priv, cdclk_config); in intel_cdclk_get_cdclk()
86 static void intel_cdclk_set_cdclk(struct drm_i915_private *dev_priv, in intel_cdclk_set_cdclk() argument
90 dev_priv->display.funcs.cdclk->set_cdclk(dev_priv, cdclk_config, pipe); in intel_cdclk_set_cdclk()
93 static int intel_cdclk_modeset_calc_cdclk(struct drm_i915_private *dev_priv, in intel_cdclk_modeset_calc_cdclk() argument
96 return dev_priv->display.funcs.cdclk->modeset_calc_cdclk(cdclk_config); in intel_cdclk_modeset_calc_cdclk()
99 static u8 intel_cdclk_calc_voltage_level(struct drm_i915_private *dev_priv, in intel_cdclk_calc_voltage_level() argument
102 return dev_priv->display.funcs.cdclk->calc_voltage_level(cdclk); in intel_cdclk_calc_voltage_level()
105 static void fixed_133mhz_get_cdclk(struct drm_i915_private *dev_priv, in fixed_133mhz_get_cdclk() argument
111 static void fixed_200mhz_get_cdclk(struct drm_i915_private *dev_priv, in fixed_200mhz_get_cdclk() argument
117 static void fixed_266mhz_get_cdclk(struct drm_i915_private *dev_priv, in fixed_266mhz_get_cdclk() argument
123 static void fixed_333mhz_get_cdclk(struct drm_i915_private *dev_priv, in fixed_333mhz_get_cdclk() argument
129 static void fixed_400mhz_get_cdclk(struct drm_i915_private *dev_priv, in fixed_400mhz_get_cdclk() argument
135 static void fixed_450mhz_get_cdclk(struct drm_i915_private *dev_priv, in fixed_450mhz_get_cdclk() argument
141 static void i85x_get_cdclk(struct drm_i915_private *dev_priv, in i85x_get_cdclk() argument
144 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); in i85x_get_cdclk()
183 static void i915gm_get_cdclk(struct drm_i915_private *dev_priv, in i915gm_get_cdclk() argument
186 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); in i915gm_get_cdclk()
207 static void i945gm_get_cdclk(struct drm_i915_private *dev_priv, in i945gm_get_cdclk() argument
210 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); in i945gm_get_cdclk()
231 static unsigned int intel_hpll_vco(struct drm_i915_private *dev_priv) in intel_hpll_vco() argument
275 if (IS_GM45(dev_priv)) in intel_hpll_vco()
277 else if (IS_G45(dev_priv)) in intel_hpll_vco()
279 else if (IS_I965GM(dev_priv)) in intel_hpll_vco()
281 else if (IS_PINEVIEW(dev_priv)) in intel_hpll_vco()
283 else if (IS_G33(dev_priv)) in intel_hpll_vco()
288 tmp = intel_de_read(dev_priv, in intel_hpll_vco()
289 IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv) ? HPLLVCO_MOBILE : HPLLVCO); in intel_hpll_vco()
293 drm_err(&dev_priv->drm, "Bad HPLL VCO (HPLLVCO=0x%02x)\n", in intel_hpll_vco()
296 drm_dbg_kms(&dev_priv->drm, "HPLL VCO %u kHz\n", vco); in intel_hpll_vco()
301 static void g33_get_cdclk(struct drm_i915_private *dev_priv, in g33_get_cdclk() argument
304 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); in g33_get_cdclk()
313 cdclk_config->vco = intel_hpll_vco(dev_priv); in g33_get_cdclk()
344 drm_err(&dev_priv->drm, in g33_get_cdclk()
350 static void pnv_get_cdclk(struct drm_i915_private *dev_priv, in pnv_get_cdclk() argument
353 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); in pnv_get_cdclk()
372 drm_err(&dev_priv->drm, in pnv_get_cdclk()
384 static void i965gm_get_cdclk(struct drm_i915_private *dev_priv, in i965gm_get_cdclk() argument
387 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); in i965gm_get_cdclk()
395 cdclk_config->vco = intel_hpll_vco(dev_priv); in i965gm_get_cdclk()
423 drm_err(&dev_priv->drm, in i965gm_get_cdclk()
429 static void gm45_get_cdclk(struct drm_i915_private *dev_priv, in gm45_get_cdclk() argument
432 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); in gm45_get_cdclk()
436 cdclk_config->vco = intel_hpll_vco(dev_priv); in gm45_get_cdclk()
452 drm_err(&dev_priv->drm, in gm45_get_cdclk()
460 static void hsw_get_cdclk(struct drm_i915_private *dev_priv, in hsw_get_cdclk() argument
463 u32 lcpll = intel_de_read(dev_priv, LCPLL_CTL); in hsw_get_cdclk()
468 else if (intel_de_read(dev_priv, FUSE_STRAP) & HSW_CDCLK_LIMIT) in hsw_get_cdclk()
472 else if (IS_HSW_ULT(dev_priv)) in hsw_get_cdclk()
478 static int vlv_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk) in vlv_calc_cdclk() argument
480 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? in vlv_calc_cdclk()
488 if (IS_VALLEYVIEW(dev_priv) && min_cdclk > freq_320) in vlv_calc_cdclk()
498 static u8 vlv_calc_voltage_level(struct drm_i915_private *dev_priv, int cdclk) in vlv_calc_voltage_level() argument
500 if (IS_VALLEYVIEW(dev_priv)) { in vlv_calc_voltage_level()
513 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; in vlv_calc_voltage_level()
517 static void vlv_get_cdclk(struct drm_i915_private *dev_priv, in vlv_get_cdclk() argument
522 vlv_iosf_sb_get(dev_priv, in vlv_get_cdclk()
525 cdclk_config->vco = vlv_get_hpll_vco(dev_priv); in vlv_get_cdclk()
526 cdclk_config->cdclk = vlv_get_cck_clock(dev_priv, "cdclk", in vlv_get_cdclk()
530 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM); in vlv_get_cdclk()
532 vlv_iosf_sb_put(dev_priv, in vlv_get_cdclk()
535 if (IS_VALLEYVIEW(dev_priv)) in vlv_get_cdclk()
543 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv) in vlv_program_pfi_credits() argument
547 if (IS_CHERRYVIEW(dev_priv)) in vlv_program_pfi_credits()
552 if (dev_priv->display.cdclk.hw.cdclk >= dev_priv->czclk_freq) { in vlv_program_pfi_credits()
554 if (IS_CHERRYVIEW(dev_priv)) in vlv_program_pfi_credits()
566 intel_de_write(dev_priv, GCI_CONTROL, in vlv_program_pfi_credits()
569 intel_de_write(dev_priv, GCI_CONTROL, in vlv_program_pfi_credits()
576 drm_WARN_ON(&dev_priv->drm, in vlv_program_pfi_credits()
577 intel_de_read(dev_priv, GCI_CONTROL) & PFI_CREDIT_RESEND); in vlv_program_pfi_credits()
580 static void vlv_set_cdclk(struct drm_i915_private *dev_priv, in vlv_set_cdclk() argument
606 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DISPLAY_CORE); in vlv_set_cdclk()
608 vlv_iosf_sb_get(dev_priv, in vlv_set_cdclk()
613 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM); in vlv_set_cdclk()
616 vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, val); in vlv_set_cdclk()
617 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & in vlv_set_cdclk()
620 drm_err(&dev_priv->drm, in vlv_set_cdclk()
627 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, in vlv_set_cdclk()
631 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); in vlv_set_cdclk()
634 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val); in vlv_set_cdclk()
636 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) & in vlv_set_cdclk()
639 drm_err(&dev_priv->drm, in vlv_set_cdclk()
644 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC); in vlv_set_cdclk()
655 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val); in vlv_set_cdclk()
657 vlv_iosf_sb_put(dev_priv, in vlv_set_cdclk()
662 intel_update_cdclk(dev_priv); in vlv_set_cdclk()
664 vlv_program_pfi_credits(dev_priv); in vlv_set_cdclk()
666 intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref); in vlv_set_cdclk()
669 static void chv_set_cdclk(struct drm_i915_private *dev_priv, in chv_set_cdclk() argument
694 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DISPLAY_CORE); in chv_set_cdclk()
696 vlv_punit_get(dev_priv); in chv_set_cdclk()
697 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM); in chv_set_cdclk()
700 vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, val); in chv_set_cdclk()
701 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & in chv_set_cdclk()
704 drm_err(&dev_priv->drm, in chv_set_cdclk()
708 vlv_punit_put(dev_priv); in chv_set_cdclk()
710 intel_update_cdclk(dev_priv); in chv_set_cdclk()
712 vlv_program_pfi_credits(dev_priv); in chv_set_cdclk()
714 intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref); in chv_set_cdclk()
744 static void bdw_get_cdclk(struct drm_i915_private *dev_priv, in bdw_get_cdclk() argument
747 u32 lcpll = intel_de_read(dev_priv, LCPLL_CTL); in bdw_get_cdclk()
752 else if (intel_de_read(dev_priv, FUSE_STRAP) & HSW_CDCLK_LIMIT) in bdw_get_cdclk()
788 static void bdw_set_cdclk(struct drm_i915_private *dev_priv, in bdw_set_cdclk() argument
795 if (drm_WARN(&dev_priv->drm, in bdw_set_cdclk()
796 (intel_de_read(dev_priv, LCPLL_CTL) & in bdw_set_cdclk()
804 ret = snb_pcode_write(&dev_priv->uncore, BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0); in bdw_set_cdclk()
806 drm_err(&dev_priv->drm, in bdw_set_cdclk()
811 intel_de_rmw(dev_priv, LCPLL_CTL, in bdw_set_cdclk()
818 if (wait_for_us(intel_de_read(dev_priv, LCPLL_CTL) & in bdw_set_cdclk()
820 drm_err(&dev_priv->drm, "Switching to FCLK failed\n"); in bdw_set_cdclk()
822 intel_de_rmw(dev_priv, LCPLL_CTL, in bdw_set_cdclk()
825 intel_de_rmw(dev_priv, LCPLL_CTL, in bdw_set_cdclk()
828 if (wait_for_us((intel_de_read(dev_priv, LCPLL_CTL) & in bdw_set_cdclk()
830 drm_err(&dev_priv->drm, "Switching back to LCPLL failed\n"); in bdw_set_cdclk()
832 snb_pcode_write(&dev_priv->uncore, HSW_PCODE_DE_WRITE_FREQ_REQ, in bdw_set_cdclk()
835 intel_de_write(dev_priv, CDCLK_FREQ, in bdw_set_cdclk()
838 intel_update_cdclk(dev_priv); in bdw_set_cdclk()
876 static void skl_dpll0_update(struct drm_i915_private *dev_priv, in skl_dpll0_update() argument
884 val = intel_de_read(dev_priv, LCPLL1_CTL); in skl_dpll0_update()
888 if (drm_WARN_ON(&dev_priv->drm, (val & LCPLL_PLL_LOCK) == 0)) in skl_dpll0_update()
891 val = intel_de_read(dev_priv, DPLL_CTRL1); in skl_dpll0_update()
893 if (drm_WARN_ON(&dev_priv->drm, in skl_dpll0_update()
917 static void skl_get_cdclk(struct drm_i915_private *dev_priv, in skl_get_cdclk() argument
922 skl_dpll0_update(dev_priv, cdclk_config); in skl_get_cdclk()
929 cdctl = intel_de_read(dev_priv, CDCLK_CTL); in skl_get_cdclk()
984 static void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv, in skl_set_preferred_cdclk_vco() argument
987 bool changed = dev_priv->skl_preferred_vco_freq != vco; in skl_set_preferred_cdclk_vco()
989 dev_priv->skl_preferred_vco_freq = vco; in skl_set_preferred_cdclk_vco()
992 intel_update_max_cdclk(dev_priv); in skl_set_preferred_cdclk_vco()
995 static u32 skl_dpll0_link_rate(struct drm_i915_private *dev_priv, int vco) in skl_dpll0_link_rate() argument
997 drm_WARN_ON(&dev_priv->drm, vco != 8100000 && vco != 8640000); in skl_dpll0_link_rate()
1014 static void skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco) in skl_dpll0_enable() argument
1016 intel_de_rmw(dev_priv, DPLL_CTRL1, in skl_dpll0_enable()
1021 skl_dpll0_link_rate(dev_priv, vco)); in skl_dpll0_enable()
1022 intel_de_posting_read(dev_priv, DPLL_CTRL1); in skl_dpll0_enable()
1024 intel_de_rmw(dev_priv, LCPLL1_CTL, in skl_dpll0_enable()
1027 if (intel_de_wait_for_set(dev_priv, LCPLL1_CTL, LCPLL_PLL_LOCK, 5)) in skl_dpll0_enable()
1028 drm_err(&dev_priv->drm, "DPLL0 not locked\n"); in skl_dpll0_enable()
1030 dev_priv->display.cdclk.hw.vco = vco; in skl_dpll0_enable()
1033 skl_set_preferred_cdclk_vco(dev_priv, vco); in skl_dpll0_enable()
1036 static void skl_dpll0_disable(struct drm_i915_private *dev_priv) in skl_dpll0_disable() argument
1038 intel_de_rmw(dev_priv, LCPLL1_CTL, in skl_dpll0_disable()
1041 if (intel_de_wait_for_clear(dev_priv, LCPLL1_CTL, LCPLL_PLL_LOCK, 1)) in skl_dpll0_disable()
1042 drm_err(&dev_priv->drm, "Couldn't disable DPLL0\n"); in skl_dpll0_disable()
1044 dev_priv->display.cdclk.hw.vco = 0; in skl_dpll0_disable()
1047 static u32 skl_cdclk_freq_sel(struct drm_i915_private *dev_priv, in skl_cdclk_freq_sel() argument
1052 drm_WARN_ON(&dev_priv->drm, in skl_cdclk_freq_sel()
1053 cdclk != dev_priv->display.cdclk.hw.bypass); in skl_cdclk_freq_sel()
1054 drm_WARN_ON(&dev_priv->drm, vco != 0); in skl_cdclk_freq_sel()
1070 static void skl_set_cdclk(struct drm_i915_private *dev_priv, in skl_set_cdclk() argument
1087 drm_WARN_ON_ONCE(&dev_priv->drm, in skl_set_cdclk()
1088 IS_SKYLAKE(dev_priv) && vco == 8640000); in skl_set_cdclk()
1090 ret = skl_pcode_request(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL, in skl_set_cdclk()
1095 drm_err(&dev_priv->drm, in skl_set_cdclk()
1100 freq_select = skl_cdclk_freq_sel(dev_priv, cdclk, vco); in skl_set_cdclk()
1102 if (dev_priv->display.cdclk.hw.vco != 0 && in skl_set_cdclk()
1103 dev_priv->display.cdclk.hw.vco != vco) in skl_set_cdclk()
1104 skl_dpll0_disable(dev_priv); in skl_set_cdclk()
1106 cdclk_ctl = intel_de_read(dev_priv, CDCLK_CTL); in skl_set_cdclk()
1108 if (dev_priv->display.cdclk.hw.vco != vco) { in skl_set_cdclk()
1112 intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl); in skl_set_cdclk()
1117 intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl); in skl_set_cdclk()
1118 intel_de_posting_read(dev_priv, CDCLK_CTL); in skl_set_cdclk()
1120 if (dev_priv->display.cdclk.hw.vco != vco) in skl_set_cdclk()
1121 skl_dpll0_enable(dev_priv, vco); in skl_set_cdclk()
1125 intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl); in skl_set_cdclk()
1128 intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl); in skl_set_cdclk()
1132 intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl); in skl_set_cdclk()
1133 intel_de_posting_read(dev_priv, CDCLK_CTL); in skl_set_cdclk()
1136 snb_pcode_write(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL, in skl_set_cdclk()
1139 intel_update_cdclk(dev_priv); in skl_set_cdclk()
1142 static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv) in skl_sanitize_cdclk() argument
1151 if ((intel_de_read(dev_priv, SWF_ILK(0x18)) & 0x00FFFFFF) == 0) in skl_sanitize_cdclk()
1154 intel_update_cdclk(dev_priv); in skl_sanitize_cdclk()
1155 intel_cdclk_dump_config(dev_priv, &dev_priv->display.cdclk.hw, "Current CDCLK"); in skl_sanitize_cdclk()
1158 if (dev_priv->display.cdclk.hw.vco == 0 || in skl_sanitize_cdclk()
1159 dev_priv->display.cdclk.hw.cdclk == dev_priv->display.cdclk.hw.bypass) in skl_sanitize_cdclk()
1168 cdctl = intel_de_read(dev_priv, CDCLK_CTL); in skl_sanitize_cdclk()
1170 skl_cdclk_decimal(dev_priv->display.cdclk.hw.cdclk); in skl_sanitize_cdclk()
1176 drm_dbg_kms(&dev_priv->drm, "Sanitizing cdclk programmed by pre-os\n"); in skl_sanitize_cdclk()
1179 dev_priv->display.cdclk.hw.cdclk = 0; in skl_sanitize_cdclk()
1181 dev_priv->display.cdclk.hw.vco = -1; in skl_sanitize_cdclk()
1184 static void skl_cdclk_init_hw(struct drm_i915_private *dev_priv) in skl_cdclk_init_hw() argument
1188 skl_sanitize_cdclk(dev_priv); in skl_cdclk_init_hw()
1190 if (dev_priv->display.cdclk.hw.cdclk != 0 && in skl_cdclk_init_hw()
1191 dev_priv->display.cdclk.hw.vco != 0) { in skl_cdclk_init_hw()
1196 if (dev_priv->skl_preferred_vco_freq == 0) in skl_cdclk_init_hw()
1197 skl_set_preferred_cdclk_vco(dev_priv, in skl_cdclk_init_hw()
1198 dev_priv->display.cdclk.hw.vco); in skl_cdclk_init_hw()
1202 cdclk_config = dev_priv->display.cdclk.hw; in skl_cdclk_init_hw()
1204 cdclk_config.vco = dev_priv->skl_preferred_vco_freq; in skl_cdclk_init_hw()
1210 skl_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE); in skl_cdclk_init_hw()
1213 static void skl_cdclk_uninit_hw(struct drm_i915_private *dev_priv) in skl_cdclk_uninit_hw() argument
1215 struct intel_cdclk_config cdclk_config = dev_priv->display.cdclk.hw; in skl_cdclk_uninit_hw()
1221 skl_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE); in skl_cdclk_uninit_hw()
1359 static int bxt_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk) in bxt_calc_cdclk() argument
1361 const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table; in bxt_calc_cdclk()
1365 if (table[i].refclk == dev_priv->display.cdclk.hw.ref && in bxt_calc_cdclk()
1369 drm_WARN(&dev_priv->drm, 1, in bxt_calc_cdclk()
1371 min_cdclk, dev_priv->display.cdclk.hw.ref); in bxt_calc_cdclk()
1375 static int bxt_calc_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk) in bxt_calc_cdclk_pll_vco() argument
1377 const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table; in bxt_calc_cdclk_pll_vco()
1380 if (cdclk == dev_priv->display.cdclk.hw.bypass) in bxt_calc_cdclk_pll_vco()
1384 if (table[i].refclk == dev_priv->display.cdclk.hw.ref && in bxt_calc_cdclk_pll_vco()
1386 return dev_priv->display.cdclk.hw.ref * table[i].ratio; in bxt_calc_cdclk_pll_vco()
1388 drm_WARN(&dev_priv->drm, 1, "cdclk %d not valid for refclk %u\n", in bxt_calc_cdclk_pll_vco()
1389 cdclk, dev_priv->display.cdclk.hw.ref); in bxt_calc_cdclk_pll_vco()
1432 static void icl_readout_refclk(struct drm_i915_private *dev_priv, in icl_readout_refclk() argument
1435 u32 dssm = intel_de_read(dev_priv, SKL_DSSM) & ICL_DSSM_CDCLK_PLL_REFCLK_MASK; in icl_readout_refclk()
1453 static void bxt_de_pll_readout(struct drm_i915_private *dev_priv, in bxt_de_pll_readout() argument
1458 if (IS_DG2(dev_priv)) in bxt_de_pll_readout()
1460 else if (DISPLAY_VER(dev_priv) >= 11) in bxt_de_pll_readout()
1461 icl_readout_refclk(dev_priv, cdclk_config); in bxt_de_pll_readout()
1465 val = intel_de_read(dev_priv, BXT_DE_PLL_ENABLE); in bxt_de_pll_readout()
1480 if (DISPLAY_VER(dev_priv) >= 11) in bxt_de_pll_readout()
1483 ratio = intel_de_read(dev_priv, BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK; in bxt_de_pll_readout()
1488 static void bxt_get_cdclk(struct drm_i915_private *dev_priv, in bxt_get_cdclk() argument
1495 bxt_de_pll_readout(dev_priv, cdclk_config); in bxt_get_cdclk()
1497 if (DISPLAY_VER(dev_priv) >= 12) in bxt_get_cdclk()
1499 else if (DISPLAY_VER(dev_priv) >= 11) in bxt_get_cdclk()
1509 divider = intel_de_read(dev_priv, CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK; in bxt_get_cdclk()
1529 if (HAS_CDCLK_SQUASH(dev_priv)) in bxt_get_cdclk()
1530 squash_ctl = intel_de_read(dev_priv, CDCLK_SQUASH_CTL); in bxt_get_cdclk()
1551 intel_cdclk_calc_voltage_level(dev_priv, cdclk_config->cdclk); in bxt_get_cdclk()
1554 static void bxt_de_pll_disable(struct drm_i915_private *dev_priv) in bxt_de_pll_disable() argument
1556 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, 0); in bxt_de_pll_disable()
1559 if (intel_de_wait_for_clear(dev_priv, in bxt_de_pll_disable()
1561 drm_err(&dev_priv->drm, "timeout waiting for DE PLL unlock\n"); in bxt_de_pll_disable()
1563 dev_priv->display.cdclk.hw.vco = 0; in bxt_de_pll_disable()
1566 static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco) in bxt_de_pll_enable() argument
1568 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->display.cdclk.hw.ref); in bxt_de_pll_enable()
1570 intel_de_rmw(dev_priv, BXT_DE_PLL_CTL, in bxt_de_pll_enable()
1573 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE); in bxt_de_pll_enable()
1576 if (intel_de_wait_for_set(dev_priv, in bxt_de_pll_enable()
1578 drm_err(&dev_priv->drm, "timeout waiting for DE PLL lock\n"); in bxt_de_pll_enable()
1580 dev_priv->display.cdclk.hw.vco = vco; in bxt_de_pll_enable()
1583 static void icl_cdclk_pll_disable(struct drm_i915_private *dev_priv) in icl_cdclk_pll_disable() argument
1585 intel_de_rmw(dev_priv, BXT_DE_PLL_ENABLE, in icl_cdclk_pll_disable()
1589 if (intel_de_wait_for_clear(dev_priv, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1)) in icl_cdclk_pll_disable()
1590 drm_err(&dev_priv->drm, "timeout waiting for CDCLK PLL unlock\n"); in icl_cdclk_pll_disable()
1592 dev_priv->display.cdclk.hw.vco = 0; in icl_cdclk_pll_disable()
1595 static void icl_cdclk_pll_enable(struct drm_i915_private *dev_priv, int vco) in icl_cdclk_pll_enable() argument
1597 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->display.cdclk.hw.ref); in icl_cdclk_pll_enable()
1601 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val); in icl_cdclk_pll_enable()
1604 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val); in icl_cdclk_pll_enable()
1607 if (intel_de_wait_for_set(dev_priv, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1)) in icl_cdclk_pll_enable()
1608 drm_err(&dev_priv->drm, "timeout waiting for CDCLK PLL lock\n"); in icl_cdclk_pll_enable()
1610 dev_priv->display.cdclk.hw.vco = vco; in icl_cdclk_pll_enable()
1613 static void adlp_cdclk_pll_crawl(struct drm_i915_private *dev_priv, int vco) in adlp_cdclk_pll_crawl() argument
1615 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->display.cdclk.hw.ref); in adlp_cdclk_pll_crawl()
1620 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val); in adlp_cdclk_pll_crawl()
1624 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val); in adlp_cdclk_pll_crawl()
1627 if (intel_de_wait_for_set(dev_priv, BXT_DE_PLL_ENABLE, in adlp_cdclk_pll_crawl()
1629 drm_err(&dev_priv->drm, "timeout waiting for FREQ change request ack\n"); in adlp_cdclk_pll_crawl()
1632 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val); in adlp_cdclk_pll_crawl()
1634 dev_priv->display.cdclk.hw.vco = vco; in adlp_cdclk_pll_crawl()
1637 static u32 bxt_cdclk_cd2x_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) in bxt_cdclk_cd2x_pipe() argument
1639 if (DISPLAY_VER(dev_priv) >= 12) { in bxt_cdclk_cd2x_pipe()
1644 } else if (DISPLAY_VER(dev_priv) >= 11) { in bxt_cdclk_cd2x_pipe()
1657 static u32 bxt_cdclk_cd2x_div_sel(struct drm_i915_private *dev_priv, in bxt_cdclk_cd2x_div_sel() argument
1663 drm_WARN_ON(&dev_priv->drm, in bxt_cdclk_cd2x_div_sel()
1664 cdclk != dev_priv->display.cdclk.hw.bypass); in bxt_cdclk_cd2x_div_sel()
1665 drm_WARN_ON(&dev_priv->drm, vco != 0); in bxt_cdclk_cd2x_div_sel()
1678 static u32 cdclk_squash_waveform(struct drm_i915_private *dev_priv, in cdclk_squash_waveform() argument
1681 const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table; in cdclk_squash_waveform()
1684 if (cdclk == dev_priv->display.cdclk.hw.bypass) in cdclk_squash_waveform()
1688 if (table[i].refclk == dev_priv->display.cdclk.hw.ref && in cdclk_squash_waveform()
1692 drm_WARN(&dev_priv->drm, 1, "cdclk %d not valid for refclk %u\n", in cdclk_squash_waveform()
1693 cdclk, dev_priv->display.cdclk.hw.ref); in cdclk_squash_waveform()
1804 static void _bxt_set_cdclk(struct drm_i915_private *dev_priv, in _bxt_set_cdclk() argument
1814 if (HAS_CDCLK_CRAWL(dev_priv) && dev_priv->display.cdclk.hw.vco > 0 && vco > 0 && in _bxt_set_cdclk()
1815 !cdclk_pll_is_unknown(dev_priv->display.cdclk.hw.vco)) { in _bxt_set_cdclk()
1816 if (dev_priv->display.cdclk.hw.vco != vco) in _bxt_set_cdclk()
1817 adlp_cdclk_pll_crawl(dev_priv, vco); in _bxt_set_cdclk()
1818 } else if (DISPLAY_VER(dev_priv) >= 11) in _bxt_set_cdclk()
1819 icl_cdclk_pll_update(dev_priv, vco); in _bxt_set_cdclk()
1821 bxt_cdclk_pll_update(dev_priv, vco); in _bxt_set_cdclk()
1823 waveform = cdclk_squash_waveform(dev_priv, cdclk); in _bxt_set_cdclk()
1830 if (HAS_CDCLK_SQUASH(dev_priv)) in _bxt_set_cdclk()
1831 dg2_cdclk_squash_program(dev_priv, waveform); in _bxt_set_cdclk()
1833 val = bxt_cdclk_cd2x_div_sel(dev_priv, clock, vco) | in _bxt_set_cdclk()
1834 bxt_cdclk_cd2x_pipe(dev_priv, pipe) | in _bxt_set_cdclk()
1841 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) && in _bxt_set_cdclk()
1844 intel_de_write(dev_priv, CDCLK_CTL, val); in _bxt_set_cdclk()
1847 intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(dev_priv, pipe)); in _bxt_set_cdclk()
1850 static void bxt_set_cdclk(struct drm_i915_private *dev_priv, in bxt_set_cdclk() argument
1864 if (DISPLAY_VER(dev_priv) >= 14) in bxt_set_cdclk()
1866 else if (DISPLAY_VER(dev_priv) >= 11) in bxt_set_cdclk()
1867 ret = skl_pcode_request(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL, in bxt_set_cdclk()
1876 ret = snb_pcode_write_timeout(&dev_priv->uncore, in bxt_set_cdclk()
1881 drm_err(&dev_priv->drm, in bxt_set_cdclk()
1887 if (cdclk_compute_crawl_and_squash_midpoint(dev_priv, &dev_priv->display.cdclk.hw, in bxt_set_cdclk()
1889 _bxt_set_cdclk(dev_priv, &mid_cdclk_config, pipe); in bxt_set_cdclk()
1890 _bxt_set_cdclk(dev_priv, cdclk_config, pipe); in bxt_set_cdclk()
1892 _bxt_set_cdclk(dev_priv, cdclk_config, pipe); in bxt_set_cdclk()
1895 if (DISPLAY_VER(dev_priv) >= 14) in bxt_set_cdclk()
1900 else if (DISPLAY_VER(dev_priv) >= 11) in bxt_set_cdclk()
1901 ret = snb_pcode_write(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL, in bxt_set_cdclk()
1910 ret = snb_pcode_write_timeout(&dev_priv->uncore, in bxt_set_cdclk()
1916 drm_err(&dev_priv->drm, in bxt_set_cdclk()
1922 intel_update_cdclk(dev_priv); in bxt_set_cdclk()
1924 if (DISPLAY_VER(dev_priv) >= 11) in bxt_set_cdclk()
1929 dev_priv->display.cdclk.hw.voltage_level = cdclk_config->voltage_level; in bxt_set_cdclk()
1932 static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv) in bxt_sanitize_cdclk() argument
1937 intel_update_cdclk(dev_priv); in bxt_sanitize_cdclk()
1938 intel_cdclk_dump_config(dev_priv, &dev_priv->display.cdclk.hw, "Current CDCLK"); in bxt_sanitize_cdclk()
1940 if (dev_priv->display.cdclk.hw.vco == 0 || in bxt_sanitize_cdclk()
1941 dev_priv->display.cdclk.hw.cdclk == dev_priv->display.cdclk.hw.bypass) in bxt_sanitize_cdclk()
1950 cdctl = intel_de_read(dev_priv, CDCLK_CTL); in bxt_sanitize_cdclk()
1956 cdctl &= ~bxt_cdclk_cd2x_pipe(dev_priv, INVALID_PIPE); in bxt_sanitize_cdclk()
1959 cdclk = bxt_calc_cdclk(dev_priv, dev_priv->display.cdclk.hw.cdclk); in bxt_sanitize_cdclk()
1960 if (cdclk != dev_priv->display.cdclk.hw.cdclk) in bxt_sanitize_cdclk()
1964 vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk); in bxt_sanitize_cdclk()
1965 if (vco != dev_priv->display.cdclk.hw.vco) in bxt_sanitize_cdclk()
1971 if (HAS_CDCLK_SQUASH(dev_priv)) in bxt_sanitize_cdclk()
1972 clock = dev_priv->display.cdclk.hw.vco / 2; in bxt_sanitize_cdclk()
1974 clock = dev_priv->display.cdclk.hw.cdclk; in bxt_sanitize_cdclk()
1976 expected |= bxt_cdclk_cd2x_div_sel(dev_priv, clock, in bxt_sanitize_cdclk()
1977 dev_priv->display.cdclk.hw.vco); in bxt_sanitize_cdclk()
1983 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) && in bxt_sanitize_cdclk()
1984 dev_priv->display.cdclk.hw.cdclk >= 500000) in bxt_sanitize_cdclk()
1992 drm_dbg_kms(&dev_priv->drm, "Sanitizing cdclk programmed by pre-os\n"); in bxt_sanitize_cdclk()
1995 dev_priv->display.cdclk.hw.cdclk = 0; in bxt_sanitize_cdclk()
1998 dev_priv->display.cdclk.hw.vco = -1; in bxt_sanitize_cdclk()
2001 static void bxt_cdclk_init_hw(struct drm_i915_private *dev_priv) in bxt_cdclk_init_hw() argument
2005 bxt_sanitize_cdclk(dev_priv); in bxt_cdclk_init_hw()
2007 if (dev_priv->display.cdclk.hw.cdclk != 0 && in bxt_cdclk_init_hw()
2008 dev_priv->display.cdclk.hw.vco != 0) in bxt_cdclk_init_hw()
2011 cdclk_config = dev_priv->display.cdclk.hw; in bxt_cdclk_init_hw()
2018 cdclk_config.cdclk = bxt_calc_cdclk(dev_priv, 0); in bxt_cdclk_init_hw()
2019 cdclk_config.vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk_config.cdclk); in bxt_cdclk_init_hw()
2021 intel_cdclk_calc_voltage_level(dev_priv, cdclk_config.cdclk); in bxt_cdclk_init_hw()
2023 bxt_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE); in bxt_cdclk_init_hw()
2026 static void bxt_cdclk_uninit_hw(struct drm_i915_private *dev_priv) in bxt_cdclk_uninit_hw() argument
2028 struct intel_cdclk_config cdclk_config = dev_priv->display.cdclk.hw; in bxt_cdclk_uninit_hw()
2033 intel_cdclk_calc_voltage_level(dev_priv, cdclk_config.cdclk); in bxt_cdclk_uninit_hw()
2035 bxt_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE); in bxt_cdclk_uninit_hw()
2092 static bool intel_cdclk_can_crawl(struct drm_i915_private *dev_priv, in intel_cdclk_can_crawl() argument
2098 if (!HAS_CDCLK_CRAWL(dev_priv)) in intel_cdclk_can_crawl()
2114 static bool intel_cdclk_can_squash(struct drm_i915_private *dev_priv, in intel_cdclk_can_squash() argument
2124 if (!HAS_CDCLK_SQUASH(dev_priv)) in intel_cdclk_can_squash()
2162 static bool intel_cdclk_can_cd2x_update(struct drm_i915_private *dev_priv, in intel_cdclk_can_cd2x_update() argument
2167 if (DISPLAY_VER(dev_priv) < 10 && !IS_BROXTON(dev_priv)) in intel_cdclk_can_cd2x_update()
2176 if (HAS_CDCLK_SQUASH(dev_priv)) in intel_cdclk_can_cd2x_update()
2219 static void intel_set_cdclk(struct drm_i915_private *dev_priv, in intel_set_cdclk() argument
2225 if (!intel_cdclk_changed(&dev_priv->display.cdclk.hw, cdclk_config)) in intel_set_cdclk()
2228 if (drm_WARN_ON_ONCE(&dev_priv->drm, !dev_priv->display.funcs.cdclk->set_cdclk)) in intel_set_cdclk()
2231 intel_cdclk_dump_config(dev_priv, cdclk_config, "Changing CDCLK to"); in intel_set_cdclk()
2233 for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) { in intel_set_cdclk()
2239 intel_audio_cdclk_change_pre(dev_priv); in intel_set_cdclk()
2246 mutex_lock(&dev_priv->display.gmbus.mutex); in intel_set_cdclk()
2247 for_each_intel_dp(&dev_priv->drm, encoder) { in intel_set_cdclk()
2251 &dev_priv->display.gmbus.mutex); in intel_set_cdclk()
2254 intel_cdclk_set_cdclk(dev_priv, cdclk_config, pipe); in intel_set_cdclk()
2256 for_each_intel_dp(&dev_priv->drm, encoder) { in intel_set_cdclk()
2261 mutex_unlock(&dev_priv->display.gmbus.mutex); in intel_set_cdclk()
2263 for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) { in intel_set_cdclk()
2269 intel_audio_cdclk_change_post(dev_priv); in intel_set_cdclk()
2271 if (drm_WARN(&dev_priv->drm, in intel_set_cdclk()
2272 intel_cdclk_changed(&dev_priv->display.cdclk.hw, cdclk_config), in intel_set_cdclk()
2274 intel_cdclk_dump_config(dev_priv, &dev_priv->display.cdclk.hw, "[hw state]"); in intel_set_cdclk()
2275 intel_cdclk_dump_config(dev_priv, cdclk_config, "[sw state]"); in intel_set_cdclk()
2289 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in intel_set_cdclk_pre_plane_update() local
2302 drm_WARN_ON(&dev_priv->drm, !new_cdclk_state->base.changed); in intel_set_cdclk_pre_plane_update()
2304 intel_set_cdclk(dev_priv, &new_cdclk_state->actual, pipe); in intel_set_cdclk_pre_plane_update()
2318 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in intel_set_cdclk_post_plane_update() local
2331 drm_WARN_ON(&dev_priv->drm, !new_cdclk_state->base.changed); in intel_set_cdclk_post_plane_update()
2333 intel_set_cdclk(dev_priv, &new_cdclk_state->actual, pipe); in intel_set_cdclk_post_plane_update()
2339 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); in intel_pixel_rate_to_cdclk() local
2342 if (DISPLAY_VER(dev_priv) >= 10) in intel_pixel_rate_to_cdclk()
2344 else if (DISPLAY_VER(dev_priv) == 9 || in intel_pixel_rate_to_cdclk()
2345 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) in intel_pixel_rate_to_cdclk()
2347 else if (IS_CHERRYVIEW(dev_priv)) in intel_pixel_rate_to_cdclk()
2358 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_planes_min_cdclk() local
2362 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) in intel_planes_min_cdclk()
2370 struct drm_i915_private *dev_priv = in intel_crtc_compute_min_cdclk() local
2380 if (IS_BROADWELL(dev_priv) && hsw_crtc_state_ips_capable(crtc_state)) in intel_crtc_compute_min_cdclk()
2392 if (DISPLAY_VER(dev_priv) == 10) { in intel_crtc_compute_min_cdclk()
2395 } else if (DISPLAY_VER(dev_priv) == 9 || IS_BROADWELL(dev_priv)) { in intel_crtc_compute_min_cdclk()
2405 if (crtc_state->has_audio && DISPLAY_VER(dev_priv) >= 9) in intel_crtc_compute_min_cdclk()
2415 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && in intel_crtc_compute_min_cdclk()
2424 IS_VALLEYVIEW(dev_priv)) in intel_crtc_compute_min_cdclk()
2433 IS_GEMINILAKE(dev_priv)) in intel_crtc_compute_min_cdclk()
2456 if (IS_TIGERLAKE(dev_priv) || IS_DG2(dev_priv)) { in intel_crtc_compute_min_cdclk()
2463 dev_priv->display.cdclk.max_cdclk_freq)); in intel_crtc_compute_min_cdclk()
2472 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in intel_compute_min_cdclk() local
2498 min_cdclk = intel_bw_min_cdclk(dev_priv, bw_state); in intel_compute_min_cdclk()
2513 for_each_pipe(dev_priv, pipe) in intel_compute_min_cdclk()
2516 if (min_cdclk > dev_priv->display.cdclk.max_cdclk_freq) { in intel_compute_min_cdclk()
2517 drm_dbg_kms(&dev_priv->drm, in intel_compute_min_cdclk()
2519 min_cdclk, dev_priv->display.cdclk.max_cdclk_freq); in intel_compute_min_cdclk()
2542 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in bxt_compute_min_voltage_level() local
2568 for_each_pipe(dev_priv, pipe) in bxt_compute_min_voltage_level()
2578 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in vlv_modeset_calc_cdclk() local
2585 cdclk = vlv_calc_cdclk(dev_priv, min_cdclk); in vlv_modeset_calc_cdclk()
2589 vlv_calc_voltage_level(dev_priv, cdclk); in vlv_modeset_calc_cdclk()
2592 cdclk = vlv_calc_cdclk(dev_priv, cdclk_state->force_min_cdclk); in vlv_modeset_calc_cdclk()
2596 vlv_calc_voltage_level(dev_priv, cdclk); in vlv_modeset_calc_cdclk()
2634 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in skl_dpll0_vco() local
2641 vco = dev_priv->skl_preferred_vco_freq; in skl_dpll0_vco()
2702 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in bxt_modeset_calc_cdclk() local
2713 cdclk = bxt_calc_cdclk(dev_priv, min_cdclk); in bxt_modeset_calc_cdclk()
2714 vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk); in bxt_modeset_calc_cdclk()
2720 intel_cdclk_calc_voltage_level(dev_priv, cdclk)); in bxt_modeset_calc_cdclk()
2723 cdclk = bxt_calc_cdclk(dev_priv, cdclk_state->force_min_cdclk); in bxt_modeset_calc_cdclk()
2724 vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk); in bxt_modeset_calc_cdclk()
2729 intel_cdclk_calc_voltage_level(dev_priv, cdclk); in bxt_modeset_calc_cdclk()
2780 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in intel_atomic_get_cdclk_state() local
2783 cdclk_state = intel_atomic_get_global_obj_state(state, &dev_priv->display.cdclk.obj); in intel_atomic_get_cdclk_state()
2825 int intel_cdclk_init(struct drm_i915_private *dev_priv) in intel_cdclk_init() argument
2833 intel_atomic_global_obj_init(dev_priv, &dev_priv->display.cdclk.obj, in intel_cdclk_init()
2841 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in intel_modeset_calc_cdclk() local
2856 ret = intel_cdclk_modeset_calc_cdclk(dev_priv, new_cdclk_state); in intel_modeset_calc_cdclk()
2881 intel_cdclk_can_cd2x_update(dev_priv, in intel_modeset_calc_cdclk()
2888 crtc = intel_crtc_for_pipe(dev_priv, pipe); in intel_modeset_calc_cdclk()
2898 if (intel_cdclk_can_crawl_and_squash(dev_priv, in intel_modeset_calc_cdclk()
2901 drm_dbg_kms(&dev_priv->drm, in intel_modeset_calc_cdclk()
2903 } else if (intel_cdclk_can_squash(dev_priv, in intel_modeset_calc_cdclk()
2906 drm_dbg_kms(&dev_priv->drm, in intel_modeset_calc_cdclk()
2908 } else if (intel_cdclk_can_crawl(dev_priv, in intel_modeset_calc_cdclk()
2911 drm_dbg_kms(&dev_priv->drm, in intel_modeset_calc_cdclk()
2916 drm_dbg_kms(&dev_priv->drm, in intel_modeset_calc_cdclk()
2926 drm_dbg_kms(&dev_priv->drm, in intel_modeset_calc_cdclk()
2930 drm_dbg_kms(&dev_priv->drm, in intel_modeset_calc_cdclk()
2934 drm_dbg_kms(&dev_priv->drm, in intel_modeset_calc_cdclk()
2942 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv) in intel_compute_max_dotclk() argument
2944 int max_cdclk_freq = dev_priv->display.cdclk.max_cdclk_freq; in intel_compute_max_dotclk()
2946 if (DISPLAY_VER(dev_priv) >= 10) in intel_compute_max_dotclk()
2948 else if (DISPLAY_VER(dev_priv) == 9 || in intel_compute_max_dotclk()
2949 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) in intel_compute_max_dotclk()
2951 else if (IS_CHERRYVIEW(dev_priv)) in intel_compute_max_dotclk()
2953 else if (DISPLAY_VER(dev_priv) < 4) in intel_compute_max_dotclk()
2967 void intel_update_max_cdclk(struct drm_i915_private *dev_priv) in intel_update_max_cdclk() argument
2969 if (IS_JSL_EHL(dev_priv)) { in intel_update_max_cdclk()
2970 if (dev_priv->display.cdclk.hw.ref == 24000) in intel_update_max_cdclk()
2971 dev_priv->display.cdclk.max_cdclk_freq = 552000; in intel_update_max_cdclk()
2973 dev_priv->display.cdclk.max_cdclk_freq = 556800; in intel_update_max_cdclk()
2974 } else if (DISPLAY_VER(dev_priv) >= 11) { in intel_update_max_cdclk()
2975 if (dev_priv->display.cdclk.hw.ref == 24000) in intel_update_max_cdclk()
2976 dev_priv->display.cdclk.max_cdclk_freq = 648000; in intel_update_max_cdclk()
2978 dev_priv->display.cdclk.max_cdclk_freq = 652800; in intel_update_max_cdclk()
2979 } else if (IS_GEMINILAKE(dev_priv)) { in intel_update_max_cdclk()
2980 dev_priv->display.cdclk.max_cdclk_freq = 316800; in intel_update_max_cdclk()
2981 } else if (IS_BROXTON(dev_priv)) { in intel_update_max_cdclk()
2982 dev_priv->display.cdclk.max_cdclk_freq = 624000; in intel_update_max_cdclk()
2983 } else if (DISPLAY_VER(dev_priv) == 9) { in intel_update_max_cdclk()
2984 u32 limit = intel_de_read(dev_priv, SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK; in intel_update_max_cdclk()
2987 vco = dev_priv->skl_preferred_vco_freq; in intel_update_max_cdclk()
2988 drm_WARN_ON(&dev_priv->drm, vco != 8100000 && vco != 8640000); in intel_update_max_cdclk()
3004 dev_priv->display.cdclk.max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco); in intel_update_max_cdclk()
3005 } else if (IS_BROADWELL(dev_priv)) { in intel_update_max_cdclk()
3012 if (intel_de_read(dev_priv, FUSE_STRAP) & HSW_CDCLK_LIMIT) in intel_update_max_cdclk()
3013 dev_priv->display.cdclk.max_cdclk_freq = 450000; in intel_update_max_cdclk()
3014 else if (IS_BDW_ULX(dev_priv)) in intel_update_max_cdclk()
3015 dev_priv->display.cdclk.max_cdclk_freq = 450000; in intel_update_max_cdclk()
3016 else if (IS_BDW_ULT(dev_priv)) in intel_update_max_cdclk()
3017 dev_priv->display.cdclk.max_cdclk_freq = 540000; in intel_update_max_cdclk()
3019 dev_priv->display.cdclk.max_cdclk_freq = 675000; in intel_update_max_cdclk()
3020 } else if (IS_CHERRYVIEW(dev_priv)) { in intel_update_max_cdclk()
3021 dev_priv->display.cdclk.max_cdclk_freq = 320000; in intel_update_max_cdclk()
3022 } else if (IS_VALLEYVIEW(dev_priv)) { in intel_update_max_cdclk()
3023 dev_priv->display.cdclk.max_cdclk_freq = 400000; in intel_update_max_cdclk()
3026 dev_priv->display.cdclk.max_cdclk_freq = dev_priv->display.cdclk.hw.cdclk; in intel_update_max_cdclk()
3029 dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv); in intel_update_max_cdclk()
3031 drm_dbg(&dev_priv->drm, "Max CD clock rate: %d kHz\n", in intel_update_max_cdclk()
3032 dev_priv->display.cdclk.max_cdclk_freq); in intel_update_max_cdclk()
3034 drm_dbg(&dev_priv->drm, "Max dotclock rate: %d kHz\n", in intel_update_max_cdclk()
3035 dev_priv->max_dotclk_freq); in intel_update_max_cdclk()
3044 void intel_update_cdclk(struct drm_i915_private *dev_priv) in intel_update_cdclk() argument
3046 intel_cdclk_get_cdclk(dev_priv, &dev_priv->display.cdclk.hw); in intel_update_cdclk()
3054 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in intel_update_cdclk()
3055 intel_de_write(dev_priv, GMBUSFREQ_VLV, in intel_update_cdclk()
3056 DIV_ROUND_UP(dev_priv->display.cdclk.hw.cdclk, 1000)); in intel_update_cdclk()
3059 static int dg1_rawclk(struct drm_i915_private *dev_priv) in dg1_rawclk() argument
3065 intel_de_write(dev_priv, PCH_RAWCLK_FREQ, in dg1_rawclk()
3071 static int cnp_rawclk(struct drm_i915_private *dev_priv) in cnp_rawclk() argument
3076 if (intel_de_read(dev_priv, SFUSE_STRAP) & SFUSE_STRAP_RAW_FREQUENCY) { in cnp_rawclk()
3092 if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) in cnp_rawclk()
3096 intel_de_write(dev_priv, PCH_RAWCLK_FREQ, rawclk); in cnp_rawclk()
3100 static int pch_rawclk(struct drm_i915_private *dev_priv) in pch_rawclk() argument
3102 return (intel_de_read(dev_priv, PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000; in pch_rawclk()
3105 static int vlv_hrawclk(struct drm_i915_private *dev_priv) in vlv_hrawclk() argument
3108 return vlv_get_cck_clock_hpll(dev_priv, "hrawclk", in vlv_hrawclk()
3112 static int i9xx_hrawclk(struct drm_i915_private *dev_priv) in i9xx_hrawclk() argument
3126 clkcfg = intel_de_read(dev_priv, CLKCFG) & CLKCFG_FSB_MASK; in i9xx_hrawclk()
3128 if (IS_MOBILE(dev_priv)) { in i9xx_hrawclk()
3175 u32 intel_read_rawclk(struct drm_i915_private *dev_priv) in intel_read_rawclk() argument
3179 if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1) in intel_read_rawclk()
3180 freq = dg1_rawclk(dev_priv); in intel_read_rawclk()
3181 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_MTP) in intel_read_rawclk()
3188 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP) in intel_read_rawclk()
3189 freq = cnp_rawclk(dev_priv); in intel_read_rawclk()
3190 else if (HAS_PCH_SPLIT(dev_priv)) in intel_read_rawclk()
3191 freq = pch_rawclk(dev_priv); in intel_read_rawclk()
3192 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in intel_read_rawclk()
3193 freq = vlv_hrawclk(dev_priv); in intel_read_rawclk()
3194 else if (DISPLAY_VER(dev_priv) >= 3) in intel_read_rawclk()
3195 freq = i9xx_hrawclk(dev_priv); in intel_read_rawclk()
3343 void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv) in intel_init_cdclk_hooks() argument
3345 if (IS_METEORLAKE(dev_priv)) { in intel_init_cdclk_hooks()
3346 dev_priv->display.funcs.cdclk = &mtl_cdclk_funcs; in intel_init_cdclk_hooks()
3347 dev_priv->display.cdclk.table = mtl_cdclk_table; in intel_init_cdclk_hooks()
3348 } else if (IS_DG2(dev_priv)) { in intel_init_cdclk_hooks()
3349 dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs; in intel_init_cdclk_hooks()
3350 dev_priv->display.cdclk.table = dg2_cdclk_table; in intel_init_cdclk_hooks()
3351 } else if (IS_ALDERLAKE_P(dev_priv)) { in intel_init_cdclk_hooks()
3352 dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs; in intel_init_cdclk_hooks()
3354 if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) in intel_init_cdclk_hooks()
3355 dev_priv->display.cdclk.table = adlp_a_step_cdclk_table; in intel_init_cdclk_hooks()
3357 dev_priv->display.cdclk.table = adlp_cdclk_table; in intel_init_cdclk_hooks()
3358 } else if (IS_ROCKETLAKE(dev_priv)) { in intel_init_cdclk_hooks()
3359 dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs; in intel_init_cdclk_hooks()
3360 dev_priv->display.cdclk.table = rkl_cdclk_table; in intel_init_cdclk_hooks()
3361 } else if (DISPLAY_VER(dev_priv) >= 12) { in intel_init_cdclk_hooks()
3362 dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs; in intel_init_cdclk_hooks()
3363 dev_priv->display.cdclk.table = icl_cdclk_table; in intel_init_cdclk_hooks()
3364 } else if (IS_JSL_EHL(dev_priv)) { in intel_init_cdclk_hooks()
3365 dev_priv->display.funcs.cdclk = &ehl_cdclk_funcs; in intel_init_cdclk_hooks()
3366 dev_priv->display.cdclk.table = icl_cdclk_table; in intel_init_cdclk_hooks()
3367 } else if (DISPLAY_VER(dev_priv) >= 11) { in intel_init_cdclk_hooks()
3368 dev_priv->display.funcs.cdclk = &icl_cdclk_funcs; in intel_init_cdclk_hooks()
3369 dev_priv->display.cdclk.table = icl_cdclk_table; in intel_init_cdclk_hooks()
3370 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { in intel_init_cdclk_hooks()
3371 dev_priv->display.funcs.cdclk = &bxt_cdclk_funcs; in intel_init_cdclk_hooks()
3372 if (IS_GEMINILAKE(dev_priv)) in intel_init_cdclk_hooks()
3373 dev_priv->display.cdclk.table = glk_cdclk_table; in intel_init_cdclk_hooks()
3375 dev_priv->display.cdclk.table = bxt_cdclk_table; in intel_init_cdclk_hooks()
3376 } else if (DISPLAY_VER(dev_priv) == 9) { in intel_init_cdclk_hooks()
3377 dev_priv->display.funcs.cdclk = &skl_cdclk_funcs; in intel_init_cdclk_hooks()
3378 } else if (IS_BROADWELL(dev_priv)) { in intel_init_cdclk_hooks()
3379 dev_priv->display.funcs.cdclk = &bdw_cdclk_funcs; in intel_init_cdclk_hooks()
3380 } else if (IS_HASWELL(dev_priv)) { in intel_init_cdclk_hooks()
3381 dev_priv->display.funcs.cdclk = &hsw_cdclk_funcs; in intel_init_cdclk_hooks()
3382 } else if (IS_CHERRYVIEW(dev_priv)) { in intel_init_cdclk_hooks()
3383 dev_priv->display.funcs.cdclk = &chv_cdclk_funcs; in intel_init_cdclk_hooks()
3384 } else if (IS_VALLEYVIEW(dev_priv)) { in intel_init_cdclk_hooks()
3385 dev_priv->display.funcs.cdclk = &vlv_cdclk_funcs; in intel_init_cdclk_hooks()
3386 } else if (IS_SANDYBRIDGE(dev_priv) || IS_IVYBRIDGE(dev_priv)) { in intel_init_cdclk_hooks()
3387 dev_priv->display.funcs.cdclk = &fixed_400mhz_cdclk_funcs; in intel_init_cdclk_hooks()
3388 } else if (IS_IRONLAKE(dev_priv)) { in intel_init_cdclk_hooks()
3389 dev_priv->display.funcs.cdclk = &ilk_cdclk_funcs; in intel_init_cdclk_hooks()
3390 } else if (IS_GM45(dev_priv)) { in intel_init_cdclk_hooks()
3391 dev_priv->display.funcs.cdclk = &gm45_cdclk_funcs; in intel_init_cdclk_hooks()
3392 } else if (IS_G45(dev_priv)) { in intel_init_cdclk_hooks()
3393 dev_priv->display.funcs.cdclk = &g33_cdclk_funcs; in intel_init_cdclk_hooks()
3394 } else if (IS_I965GM(dev_priv)) { in intel_init_cdclk_hooks()
3395 dev_priv->display.funcs.cdclk = &i965gm_cdclk_funcs; in intel_init_cdclk_hooks()
3396 } else if (IS_I965G(dev_priv)) { in intel_init_cdclk_hooks()
3397 dev_priv->display.funcs.cdclk = &fixed_400mhz_cdclk_funcs; in intel_init_cdclk_hooks()
3398 } else if (IS_PINEVIEW(dev_priv)) { in intel_init_cdclk_hooks()
3399 dev_priv->display.funcs.cdclk = &pnv_cdclk_funcs; in intel_init_cdclk_hooks()
3400 } else if (IS_G33(dev_priv)) { in intel_init_cdclk_hooks()
3401 dev_priv->display.funcs.cdclk = &g33_cdclk_funcs; in intel_init_cdclk_hooks()
3402 } else if (IS_I945GM(dev_priv)) { in intel_init_cdclk_hooks()
3403 dev_priv->display.funcs.cdclk = &i945gm_cdclk_funcs; in intel_init_cdclk_hooks()
3404 } else if (IS_I945G(dev_priv)) { in intel_init_cdclk_hooks()
3405 dev_priv->display.funcs.cdclk = &fixed_400mhz_cdclk_funcs; in intel_init_cdclk_hooks()
3406 } else if (IS_I915GM(dev_priv)) { in intel_init_cdclk_hooks()
3407 dev_priv->display.funcs.cdclk = &i915gm_cdclk_funcs; in intel_init_cdclk_hooks()
3408 } else if (IS_I915G(dev_priv)) { in intel_init_cdclk_hooks()
3409 dev_priv->display.funcs.cdclk = &i915g_cdclk_funcs; in intel_init_cdclk_hooks()
3410 } else if (IS_I865G(dev_priv)) { in intel_init_cdclk_hooks()
3411 dev_priv->display.funcs.cdclk = &i865g_cdclk_funcs; in intel_init_cdclk_hooks()
3412 } else if (IS_I85X(dev_priv)) { in intel_init_cdclk_hooks()
3413 dev_priv->display.funcs.cdclk = &i85x_cdclk_funcs; in intel_init_cdclk_hooks()
3414 } else if (IS_I845G(dev_priv)) { in intel_init_cdclk_hooks()
3415 dev_priv->display.funcs.cdclk = &i845g_cdclk_funcs; in intel_init_cdclk_hooks()
3416 } else if (IS_I830(dev_priv)) { in intel_init_cdclk_hooks()
3417 dev_priv->display.funcs.cdclk = &i830_cdclk_funcs; in intel_init_cdclk_hooks()
3420 if (drm_WARN(&dev_priv->drm, !dev_priv->display.funcs.cdclk, in intel_init_cdclk_hooks()
3422 dev_priv->display.funcs.cdclk = &i830_cdclk_funcs; in intel_init_cdclk_hooks()