Lines Matching refs:display
83 dev_priv->display.funcs.cdclk->get_cdclk(dev_priv, cdclk_config); in intel_cdclk_get_cdclk()
90 dev_priv->display.funcs.cdclk->set_cdclk(dev_priv, cdclk_config, pipe); in intel_cdclk_set_cdclk()
96 return dev_priv->display.funcs.cdclk->modeset_calc_cdclk(cdclk_config); in intel_cdclk_modeset_calc_cdclk()
102 return dev_priv->display.funcs.cdclk->calc_voltage_level(cdclk); in intel_cdclk_calc_voltage_level()
552 if (dev_priv->display.cdclk.hw.cdclk >= dev_priv->czclk_freq) { in vlv_program_pfi_credits()
1030 dev_priv->display.cdclk.hw.vco = vco; in skl_dpll0_enable()
1044 dev_priv->display.cdclk.hw.vco = 0; in skl_dpll0_disable()
1053 cdclk != dev_priv->display.cdclk.hw.bypass); in skl_cdclk_freq_sel()
1102 if (dev_priv->display.cdclk.hw.vco != 0 && in skl_set_cdclk()
1103 dev_priv->display.cdclk.hw.vco != vco) in skl_set_cdclk()
1108 if (dev_priv->display.cdclk.hw.vco != vco) { in skl_set_cdclk()
1120 if (dev_priv->display.cdclk.hw.vco != vco) in skl_set_cdclk()
1155 intel_cdclk_dump_config(dev_priv, &dev_priv->display.cdclk.hw, "Current CDCLK"); in skl_sanitize_cdclk()
1158 if (dev_priv->display.cdclk.hw.vco == 0 || in skl_sanitize_cdclk()
1159 dev_priv->display.cdclk.hw.cdclk == dev_priv->display.cdclk.hw.bypass) in skl_sanitize_cdclk()
1170 skl_cdclk_decimal(dev_priv->display.cdclk.hw.cdclk); in skl_sanitize_cdclk()
1179 dev_priv->display.cdclk.hw.cdclk = 0; in skl_sanitize_cdclk()
1181 dev_priv->display.cdclk.hw.vco = -1; in skl_sanitize_cdclk()
1190 if (dev_priv->display.cdclk.hw.cdclk != 0 && in skl_cdclk_init_hw()
1191 dev_priv->display.cdclk.hw.vco != 0) { in skl_cdclk_init_hw()
1198 dev_priv->display.cdclk.hw.vco); in skl_cdclk_init_hw()
1202 cdclk_config = dev_priv->display.cdclk.hw; in skl_cdclk_init_hw()
1215 struct intel_cdclk_config cdclk_config = dev_priv->display.cdclk.hw; in skl_cdclk_uninit_hw()
1361 const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table; in bxt_calc_cdclk()
1365 if (table[i].refclk == dev_priv->display.cdclk.hw.ref && in bxt_calc_cdclk()
1371 min_cdclk, dev_priv->display.cdclk.hw.ref); in bxt_calc_cdclk()
1377 const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table; in bxt_calc_cdclk_pll_vco()
1380 if (cdclk == dev_priv->display.cdclk.hw.bypass) in bxt_calc_cdclk_pll_vco()
1384 if (table[i].refclk == dev_priv->display.cdclk.hw.ref && in bxt_calc_cdclk_pll_vco()
1386 return dev_priv->display.cdclk.hw.ref * table[i].ratio; in bxt_calc_cdclk_pll_vco()
1389 cdclk, dev_priv->display.cdclk.hw.ref); in bxt_calc_cdclk_pll_vco()
1563 dev_priv->display.cdclk.hw.vco = 0; in bxt_de_pll_disable()
1568 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->display.cdclk.hw.ref); in bxt_de_pll_enable()
1580 dev_priv->display.cdclk.hw.vco = vco; in bxt_de_pll_enable()
1592 dev_priv->display.cdclk.hw.vco = 0; in icl_cdclk_pll_disable()
1597 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->display.cdclk.hw.ref); in icl_cdclk_pll_enable()
1610 dev_priv->display.cdclk.hw.vco = vco; in icl_cdclk_pll_enable()
1615 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->display.cdclk.hw.ref); in adlp_cdclk_pll_crawl()
1634 dev_priv->display.cdclk.hw.vco = vco; in adlp_cdclk_pll_crawl()
1664 cdclk != dev_priv->display.cdclk.hw.bypass); in bxt_cdclk_cd2x_div_sel()
1681 const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table; in cdclk_squash_waveform()
1684 if (cdclk == dev_priv->display.cdclk.hw.bypass) in cdclk_squash_waveform()
1688 if (table[i].refclk == dev_priv->display.cdclk.hw.ref && in cdclk_squash_waveform()
1693 cdclk, dev_priv->display.cdclk.hw.ref); in cdclk_squash_waveform()
1700 if (i915->display.cdclk.hw.vco != 0 && in icl_cdclk_pll_update()
1701 i915->display.cdclk.hw.vco != vco) in icl_cdclk_pll_update()
1704 if (i915->display.cdclk.hw.vco != vco) in icl_cdclk_pll_update()
1710 if (i915->display.cdclk.hw.vco != 0 && in bxt_cdclk_pll_update()
1711 i915->display.cdclk.hw.vco != vco) in bxt_cdclk_pll_update()
1714 if (i915->display.cdclk.hw.vco != vco) in bxt_cdclk_pll_update()
1797 i915->display.cdclk.max_cdclk_freq); in cdclk_compute_crawl_and_squash_midpoint()
1814 if (HAS_CDCLK_CRAWL(dev_priv) && dev_priv->display.cdclk.hw.vco > 0 && vco > 0 && in _bxt_set_cdclk()
1815 !cdclk_pll_is_unknown(dev_priv->display.cdclk.hw.vco)) { in _bxt_set_cdclk()
1816 if (dev_priv->display.cdclk.hw.vco != vco) in _bxt_set_cdclk()
1887 if (cdclk_compute_crawl_and_squash_midpoint(dev_priv, &dev_priv->display.cdclk.hw, in bxt_set_cdclk()
1929 dev_priv->display.cdclk.hw.voltage_level = cdclk_config->voltage_level; in bxt_set_cdclk()
1938 intel_cdclk_dump_config(dev_priv, &dev_priv->display.cdclk.hw, "Current CDCLK"); in bxt_sanitize_cdclk()
1940 if (dev_priv->display.cdclk.hw.vco == 0 || in bxt_sanitize_cdclk()
1941 dev_priv->display.cdclk.hw.cdclk == dev_priv->display.cdclk.hw.bypass) in bxt_sanitize_cdclk()
1959 cdclk = bxt_calc_cdclk(dev_priv, dev_priv->display.cdclk.hw.cdclk); in bxt_sanitize_cdclk()
1960 if (cdclk != dev_priv->display.cdclk.hw.cdclk) in bxt_sanitize_cdclk()
1965 if (vco != dev_priv->display.cdclk.hw.vco) in bxt_sanitize_cdclk()
1972 clock = dev_priv->display.cdclk.hw.vco / 2; in bxt_sanitize_cdclk()
1974 clock = dev_priv->display.cdclk.hw.cdclk; in bxt_sanitize_cdclk()
1977 dev_priv->display.cdclk.hw.vco); in bxt_sanitize_cdclk()
1984 dev_priv->display.cdclk.hw.cdclk >= 500000) in bxt_sanitize_cdclk()
1995 dev_priv->display.cdclk.hw.cdclk = 0; in bxt_sanitize_cdclk()
1998 dev_priv->display.cdclk.hw.vco = -1; in bxt_sanitize_cdclk()
2007 if (dev_priv->display.cdclk.hw.cdclk != 0 && in bxt_cdclk_init_hw()
2008 dev_priv->display.cdclk.hw.vco != 0) in bxt_cdclk_init_hw()
2011 cdclk_config = dev_priv->display.cdclk.hw; in bxt_cdclk_init_hw()
2028 struct intel_cdclk_config cdclk_config = dev_priv->display.cdclk.hw; in bxt_cdclk_uninit_hw()
2225 if (!intel_cdclk_changed(&dev_priv->display.cdclk.hw, cdclk_config)) in intel_set_cdclk()
2228 if (drm_WARN_ON_ONCE(&dev_priv->drm, !dev_priv->display.funcs.cdclk->set_cdclk)) in intel_set_cdclk()
2246 mutex_lock(&dev_priv->display.gmbus.mutex); in intel_set_cdclk()
2251 &dev_priv->display.gmbus.mutex); in intel_set_cdclk()
2261 mutex_unlock(&dev_priv->display.gmbus.mutex); in intel_set_cdclk()
2272 intel_cdclk_changed(&dev_priv->display.cdclk.hw, cdclk_config), in intel_set_cdclk()
2274 intel_cdclk_dump_config(dev_priv, &dev_priv->display.cdclk.hw, "[hw state]"); in intel_set_cdclk()
2463 dev_priv->display.cdclk.max_cdclk_freq)); in intel_crtc_compute_min_cdclk()
2516 if (min_cdclk > dev_priv->display.cdclk.max_cdclk_freq) { in intel_compute_min_cdclk()
2519 min_cdclk, dev_priv->display.cdclk.max_cdclk_freq); in intel_compute_min_cdclk()
2783 cdclk_state = intel_atomic_get_global_obj_state(state, &dev_priv->display.cdclk.obj); in intel_atomic_get_cdclk_state()
2833 intel_atomic_global_obj_init(dev_priv, &dev_priv->display.cdclk.obj, in intel_cdclk_init()
2944 int max_cdclk_freq = dev_priv->display.cdclk.max_cdclk_freq; in intel_compute_max_dotclk()
2970 if (dev_priv->display.cdclk.hw.ref == 24000) in intel_update_max_cdclk()
2971 dev_priv->display.cdclk.max_cdclk_freq = 552000; in intel_update_max_cdclk()
2973 dev_priv->display.cdclk.max_cdclk_freq = 556800; in intel_update_max_cdclk()
2975 if (dev_priv->display.cdclk.hw.ref == 24000) in intel_update_max_cdclk()
2976 dev_priv->display.cdclk.max_cdclk_freq = 648000; in intel_update_max_cdclk()
2978 dev_priv->display.cdclk.max_cdclk_freq = 652800; in intel_update_max_cdclk()
2980 dev_priv->display.cdclk.max_cdclk_freq = 316800; in intel_update_max_cdclk()
2982 dev_priv->display.cdclk.max_cdclk_freq = 624000; in intel_update_max_cdclk()
3004 dev_priv->display.cdclk.max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco); in intel_update_max_cdclk()
3013 dev_priv->display.cdclk.max_cdclk_freq = 450000; in intel_update_max_cdclk()
3015 dev_priv->display.cdclk.max_cdclk_freq = 450000; in intel_update_max_cdclk()
3017 dev_priv->display.cdclk.max_cdclk_freq = 540000; in intel_update_max_cdclk()
3019 dev_priv->display.cdclk.max_cdclk_freq = 675000; in intel_update_max_cdclk()
3021 dev_priv->display.cdclk.max_cdclk_freq = 320000; in intel_update_max_cdclk()
3023 dev_priv->display.cdclk.max_cdclk_freq = 400000; in intel_update_max_cdclk()
3026 dev_priv->display.cdclk.max_cdclk_freq = dev_priv->display.cdclk.hw.cdclk; in intel_update_max_cdclk()
3032 dev_priv->display.cdclk.max_cdclk_freq); in intel_update_max_cdclk()
3046 intel_cdclk_get_cdclk(dev_priv, &dev_priv->display.cdclk.hw); in intel_update_cdclk()
3056 DIV_ROUND_UP(dev_priv->display.cdclk.hw.cdclk, 1000)); in intel_update_cdclk()
3346 dev_priv->display.funcs.cdclk = &mtl_cdclk_funcs; in intel_init_cdclk_hooks()
3347 dev_priv->display.cdclk.table = mtl_cdclk_table; in intel_init_cdclk_hooks()
3349 dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs; in intel_init_cdclk_hooks()
3350 dev_priv->display.cdclk.table = dg2_cdclk_table; in intel_init_cdclk_hooks()
3352 dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs; in intel_init_cdclk_hooks()
3355 dev_priv->display.cdclk.table = adlp_a_step_cdclk_table; in intel_init_cdclk_hooks()
3357 dev_priv->display.cdclk.table = adlp_cdclk_table; in intel_init_cdclk_hooks()
3359 dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs; in intel_init_cdclk_hooks()
3360 dev_priv->display.cdclk.table = rkl_cdclk_table; in intel_init_cdclk_hooks()
3362 dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs; in intel_init_cdclk_hooks()
3363 dev_priv->display.cdclk.table = icl_cdclk_table; in intel_init_cdclk_hooks()
3365 dev_priv->display.funcs.cdclk = &ehl_cdclk_funcs; in intel_init_cdclk_hooks()
3366 dev_priv->display.cdclk.table = icl_cdclk_table; in intel_init_cdclk_hooks()
3368 dev_priv->display.funcs.cdclk = &icl_cdclk_funcs; in intel_init_cdclk_hooks()
3369 dev_priv->display.cdclk.table = icl_cdclk_table; in intel_init_cdclk_hooks()
3371 dev_priv->display.funcs.cdclk = &bxt_cdclk_funcs; in intel_init_cdclk_hooks()
3373 dev_priv->display.cdclk.table = glk_cdclk_table; in intel_init_cdclk_hooks()
3375 dev_priv->display.cdclk.table = bxt_cdclk_table; in intel_init_cdclk_hooks()
3377 dev_priv->display.funcs.cdclk = &skl_cdclk_funcs; in intel_init_cdclk_hooks()
3379 dev_priv->display.funcs.cdclk = &bdw_cdclk_funcs; in intel_init_cdclk_hooks()
3381 dev_priv->display.funcs.cdclk = &hsw_cdclk_funcs; in intel_init_cdclk_hooks()
3383 dev_priv->display.funcs.cdclk = &chv_cdclk_funcs; in intel_init_cdclk_hooks()
3385 dev_priv->display.funcs.cdclk = &vlv_cdclk_funcs; in intel_init_cdclk_hooks()
3387 dev_priv->display.funcs.cdclk = &fixed_400mhz_cdclk_funcs; in intel_init_cdclk_hooks()
3389 dev_priv->display.funcs.cdclk = &ilk_cdclk_funcs; in intel_init_cdclk_hooks()
3391 dev_priv->display.funcs.cdclk = &gm45_cdclk_funcs; in intel_init_cdclk_hooks()
3393 dev_priv->display.funcs.cdclk = &g33_cdclk_funcs; in intel_init_cdclk_hooks()
3395 dev_priv->display.funcs.cdclk = &i965gm_cdclk_funcs; in intel_init_cdclk_hooks()
3397 dev_priv->display.funcs.cdclk = &fixed_400mhz_cdclk_funcs; in intel_init_cdclk_hooks()
3399 dev_priv->display.funcs.cdclk = &pnv_cdclk_funcs; in intel_init_cdclk_hooks()
3401 dev_priv->display.funcs.cdclk = &g33_cdclk_funcs; in intel_init_cdclk_hooks()
3403 dev_priv->display.funcs.cdclk = &i945gm_cdclk_funcs; in intel_init_cdclk_hooks()
3405 dev_priv->display.funcs.cdclk = &fixed_400mhz_cdclk_funcs; in intel_init_cdclk_hooks()
3407 dev_priv->display.funcs.cdclk = &i915gm_cdclk_funcs; in intel_init_cdclk_hooks()
3409 dev_priv->display.funcs.cdclk = &i915g_cdclk_funcs; in intel_init_cdclk_hooks()
3411 dev_priv->display.funcs.cdclk = &i865g_cdclk_funcs; in intel_init_cdclk_hooks()
3413 dev_priv->display.funcs.cdclk = &i85x_cdclk_funcs; in intel_init_cdclk_hooks()
3415 dev_priv->display.funcs.cdclk = &i845g_cdclk_funcs; in intel_init_cdclk_hooks()
3417 dev_priv->display.funcs.cdclk = &i830_cdclk_funcs; in intel_init_cdclk_hooks()
3420 if (drm_WARN(&dev_priv->drm, !dev_priv->display.funcs.cdclk, in intel_init_cdclk_hooks()
3422 dev_priv->display.funcs.cdclk = &i830_cdclk_funcs; in intel_init_cdclk_hooks()