Lines Matching refs:IS_CHERRYVIEW
275 if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))) in intel_update_czclk()
2236 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { in valleyview_crtc_enable()
2247 if (IS_CHERRYVIEW(dev_priv)) in valleyview_crtc_enable()
2356 if (IS_CHERRYVIEW(dev_priv)) in i9xx_crtc_disable()
2781 return IS_DISPLAY_VER(dev_priv, 5, 7) || IS_CHERRYVIEW(dev_priv); in intel_cpu_transcoder_has_m2_n2()
3000 IS_CHERRYVIEW(dev_priv)) { in i9xx_set_pipeconf()
3033 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && in i9xx_set_pipeconf()
3206 IS_CHERRYVIEW(dev_priv)) { in i9xx_get_pipe_config()
3223 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && in i9xx_get_pipe_config()
3231 if (IS_CHERRYVIEW(dev_priv)) in i9xx_get_pipe_config()
3248 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A) in i9xx_get_pipe_config()
3270 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) { in i9xx_get_pipe_config()
3282 if (IS_CHERRYVIEW(dev_priv)) in i9xx_get_pipe_config()
4923 IS_CHERRYVIEW(dev_priv))) in compute_baseline_pipe_bpp()
5155 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in intel_crtc_prepare_cleared_state()
5499 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in fastboot_enabled()
5738 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in intel_pipe_config_compare()
5771 if (IS_CHERRYVIEW(dev_priv)) in intel_pipe_config_compare()
6152 IS_CHERRYVIEW(dev_priv) || IS_VALLEYVIEW(dev_priv) || in active_planes_affects_min_cdclk()
7994 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { in intel_setup_outputs()
8029 if (IS_CHERRYVIEW(dev_priv)) { in intel_setup_outputs()
8335 } else if (IS_CHERRYVIEW(dev_priv) || in intel_init_display_hooks()