Lines Matching refs:dpll
312 int pnv_calc_dpll_params(int refclk, struct dpll *clock) in pnv_calc_dpll_params()
324 static u32 i9xx_dpll_compute_m(const struct dpll *dpll) in i9xx_dpll_compute_m() argument
326 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); in i9xx_dpll_compute_m()
329 int i9xx_calc_dpll_params(int refclk, struct dpll *clock) in i9xx_calc_dpll_params()
341 int vlv_calc_dpll_params(int refclk, struct dpll *clock) in vlv_calc_dpll_params()
353 int chv_calc_dpll_params(int refclk, struct dpll *clock) in chv_calc_dpll_params()
372 const struct dpll *clock) in intel_pll_is_valid()
443 const struct dpll *match_clock, in i9xx_find_best_dpll()
444 struct dpll *best_clock) in i9xx_find_best_dpll()
447 struct dpll clock; in i9xx_find_best_dpll()
501 const struct dpll *match_clock, in pnv_find_best_dpll()
502 struct dpll *best_clock) in pnv_find_best_dpll()
505 struct dpll clock; in pnv_find_best_dpll()
557 const struct dpll *match_clock, in g4x_find_best_dpll()
558 struct dpll *best_clock) in g4x_find_best_dpll()
561 struct dpll clock; in g4x_find_best_dpll()
608 const struct dpll *calculated_clock, in vlv_PLL_is_optimal()
609 const struct dpll *best_clock, in vlv_PLL_is_optimal()
651 const struct dpll *match_clock, in vlv_find_best_dpll()
652 struct dpll *best_clock) in vlv_find_best_dpll()
656 struct dpll clock; in vlv_find_best_dpll()
709 const struct dpll *match_clock, in chv_find_best_dpll()
710 struct dpll *best_clock) in chv_find_best_dpll()
715 struct dpll clock; in chv_find_best_dpll()
765 struct dpll *best_clock) in bxt_find_best_dpll()
775 u32 i9xx_dpll_compute_fp(const struct dpll *dpll) in i9xx_dpll_compute_fp() argument
777 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; in i9xx_dpll_compute_fp()
780 static u32 pnv_dpll_compute_fp(const struct dpll *dpll) in pnv_dpll_compute_fp() argument
782 return (1 << dpll->n) << 16 | dpll->m2; in pnv_dpll_compute_fp()
786 const struct dpll *clock, in i9xx_update_pll_dividers()
787 const struct dpll *reduced_clock) in i9xx_update_pll_dividers()
806 const struct dpll *clock, in i9xx_compute_dpll()
807 const struct dpll *reduced_clock) in i9xx_compute_dpll()
811 u32 dpll; in i9xx_compute_dpll() local
815 dpll = DPLL_VGA_MODE_DIS; in i9xx_compute_dpll()
818 dpll |= DPLLB_MODE_LVDS; in i9xx_compute_dpll()
820 dpll |= DPLLB_MODE_DAC_SERIAL; in i9xx_compute_dpll()
824 dpll |= (crtc_state->pixel_multiplier - 1) in i9xx_compute_dpll()
830 dpll |= DPLL_SDVO_HIGH_SPEED; in i9xx_compute_dpll()
833 dpll |= DPLL_SDVO_HIGH_SPEED; in i9xx_compute_dpll()
837 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; in i9xx_compute_dpll()
838 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; in i9xx_compute_dpll()
840 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; in i9xx_compute_dpll()
843 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; in i9xx_compute_dpll()
849 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; in i9xx_compute_dpll()
852 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; in i9xx_compute_dpll()
855 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; in i9xx_compute_dpll()
858 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; in i9xx_compute_dpll()
864 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); in i9xx_compute_dpll()
867 dpll |= PLL_REF_INPUT_TVCLKINBC; in i9xx_compute_dpll()
870 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; in i9xx_compute_dpll()
872 dpll |= PLL_REF_INPUT_DREFCLK; in i9xx_compute_dpll()
874 dpll |= DPLL_VCO_ENABLE; in i9xx_compute_dpll()
875 crtc_state->dpll_hw_state.dpll = dpll; in i9xx_compute_dpll()
885 const struct dpll *clock, in i8xx_compute_dpll()
886 const struct dpll *reduced_clock) in i8xx_compute_dpll()
890 u32 dpll; in i8xx_compute_dpll() local
894 dpll = DPLL_VGA_MODE_DIS; in i8xx_compute_dpll()
897 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; in i8xx_compute_dpll()
900 dpll |= PLL_P1_DIVIDE_BY_TWO; in i8xx_compute_dpll()
902 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; in i8xx_compute_dpll()
904 dpll |= PLL_P2_DIVIDE_BY_4; in i8xx_compute_dpll()
923 dpll |= DPLL_DVO_2X_MODE; in i8xx_compute_dpll()
927 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; in i8xx_compute_dpll()
929 dpll |= PLL_REF_INPUT_DREFCLK; in i8xx_compute_dpll()
931 dpll |= DPLL_VCO_ENABLE; in i8xx_compute_dpll()
932 crtc_state->dpll_hw_state.dpll = dpll; in i8xx_compute_dpll()
998 static bool ilk_needs_fb_cb_tune(const struct dpll *dpll, int factor) in ilk_needs_fb_cb_tune() argument
1000 return dpll->m < factor * dpll->n; in ilk_needs_fb_cb_tune()
1004 const struct dpll *clock, in ilk_update_pll_dividers()
1005 const struct dpll *reduced_clock) in ilk_update_pll_dividers()
1037 const struct dpll *clock, in ilk_compute_dpll()
1038 const struct dpll *reduced_clock) in ilk_compute_dpll()
1042 u32 dpll; in ilk_compute_dpll() local
1046 dpll = 0; in ilk_compute_dpll()
1049 dpll |= DPLLB_MODE_LVDS; in ilk_compute_dpll()
1051 dpll |= DPLLB_MODE_DAC_SERIAL; in ilk_compute_dpll()
1053 dpll |= (crtc_state->pixel_multiplier - 1) in ilk_compute_dpll()
1058 dpll |= DPLL_SDVO_HIGH_SPEED; in ilk_compute_dpll()
1061 dpll |= DPLL_SDVO_HIGH_SPEED; in ilk_compute_dpll()
1079 dpll |= DPLL_SDVO_HIGH_SPEED; in ilk_compute_dpll()
1082 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; in ilk_compute_dpll()
1084 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; in ilk_compute_dpll()
1088 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; in ilk_compute_dpll()
1091 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; in ilk_compute_dpll()
1094 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; in ilk_compute_dpll()
1097 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; in ilk_compute_dpll()
1104 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; in ilk_compute_dpll()
1106 dpll |= PLL_REF_INPUT_DREFCLK; in ilk_compute_dpll()
1108 dpll |= DPLL_VCO_ENABLE; in ilk_compute_dpll()
1110 crtc_state->dpll_hw_state.dpll = dpll; in ilk_compute_dpll()
1152 refclk, NULL, &crtc_state->dpll)) in ilk_crtc_compute_clock()
1155 ilk_compute_dpll(crtc_state, &crtc_state->dpll, in ilk_crtc_compute_clock()
1156 &crtc_state->dpll); in ilk_crtc_compute_clock()
1162 crtc_state->port_clock = crtc_state->dpll.dot; in ilk_crtc_compute_clock()
1185 crtc_state->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV | in vlv_compute_dpll()
1188 crtc_state->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; in vlv_compute_dpll()
1192 crtc_state->dpll_hw_state.dpll |= DPLL_VCO_ENABLE | in vlv_compute_dpll()
1203 crtc_state->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV | in chv_compute_dpll()
1206 crtc_state->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; in chv_compute_dpll()
1210 crtc_state->dpll_hw_state.dpll |= DPLL_VCO_ENABLE; in chv_compute_dpll()
1226 refclk, NULL, &crtc_state->dpll)) in chv_crtc_compute_clock()
1235 crtc_state->port_clock = crtc_state->dpll.dot; in chv_crtc_compute_clock()
1251 refclk, NULL, &crtc_state->dpll)) { in vlv_crtc_compute_clock()
1261 crtc_state->port_clock = crtc_state->dpll.dot; in vlv_crtc_compute_clock()
1300 refclk, NULL, &crtc_state->dpll)) in g4x_crtc_compute_clock()
1303 i9xx_compute_dpll(crtc_state, &crtc_state->dpll, in g4x_crtc_compute_clock()
1304 &crtc_state->dpll); in g4x_crtc_compute_clock()
1306 crtc_state->port_clock = crtc_state->dpll.dot; in g4x_crtc_compute_clock()
1338 refclk, NULL, &crtc_state->dpll)) in pnv_crtc_compute_clock()
1341 i9xx_compute_dpll(crtc_state, &crtc_state->dpll, in pnv_crtc_compute_clock()
1342 &crtc_state->dpll); in pnv_crtc_compute_clock()
1344 crtc_state->port_clock = crtc_state->dpll.dot; in pnv_crtc_compute_clock()
1374 refclk, NULL, &crtc_state->dpll)) in i9xx_crtc_compute_clock()
1377 i9xx_compute_dpll(crtc_state, &crtc_state->dpll, in i9xx_crtc_compute_clock()
1378 &crtc_state->dpll); in i9xx_crtc_compute_clock()
1380 crtc_state->port_clock = crtc_state->dpll.dot; in i9xx_crtc_compute_clock()
1414 refclk, NULL, &crtc_state->dpll)) in i8xx_crtc_compute_clock()
1417 i8xx_compute_dpll(crtc_state, &crtc_state->dpll, in i8xx_crtc_compute_clock()
1418 &crtc_state->dpll); in i8xx_crtc_compute_clock()
1420 crtc_state->port_clock = crtc_state->dpll.dot; in i8xx_crtc_compute_clock()
1480 ret = i915->display.funcs.dpll->crtc_compute_clock(state, crtc); in intel_dpll_crtc_compute_clock()
1504 if (!i915->display.funcs.dpll->crtc_get_shared_dpll) in intel_dpll_crtc_get_shared_dpll()
1507 ret = i915->display.funcs.dpll->crtc_get_shared_dpll(state, crtc); in intel_dpll_crtc_get_shared_dpll()
1521 dev_priv->display.funcs.dpll = &dg2_dpll_funcs; in intel_dpll_init_clock_hook()
1523 dev_priv->display.funcs.dpll = &hsw_dpll_funcs; in intel_dpll_init_clock_hook()
1525 dev_priv->display.funcs.dpll = &ilk_dpll_funcs; in intel_dpll_init_clock_hook()
1527 dev_priv->display.funcs.dpll = &chv_dpll_funcs; in intel_dpll_init_clock_hook()
1529 dev_priv->display.funcs.dpll = &vlv_dpll_funcs; in intel_dpll_init_clock_hook()
1531 dev_priv->display.funcs.dpll = &g4x_dpll_funcs; in intel_dpll_init_clock_hook()
1533 dev_priv->display.funcs.dpll = &pnv_dpll_funcs; in intel_dpll_init_clock_hook()
1535 dev_priv->display.funcs.dpll = &i9xx_dpll_funcs; in intel_dpll_init_clock_hook()
1537 dev_priv->display.funcs.dpll = &i8xx_dpll_funcs; in intel_dpll_init_clock_hook()
1552 u32 dpll = crtc_state->dpll_hw_state.dpll; in i9xx_enable_pll() local
1570 intel_de_write(dev_priv, DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS); in i9xx_enable_pll()
1571 intel_de_write(dev_priv, DPLL(pipe), dpll); in i9xx_enable_pll()
1586 intel_de_write(dev_priv, DPLL(pipe), dpll); in i9xx_enable_pll()
1591 intel_de_write(dev_priv, DPLL(pipe), dpll); in i9xx_enable_pll()
1637 bestn = crtc_state->dpll.n; in vlv_prepare_pll()
1638 bestm1 = crtc_state->dpll.m1; in vlv_prepare_pll()
1639 bestm2 = crtc_state->dpll.m2; in vlv_prepare_pll()
1640 bestp1 = crtc_state->dpll.p1; in vlv_prepare_pll()
1641 bestp2 = crtc_state->dpll.p2; in vlv_prepare_pll()
1722 intel_de_write(dev_priv, DPLL(pipe), crtc_state->dpll_hw_state.dpll); in _vlv_enable_pll()
1743 crtc_state->dpll_hw_state.dpll & in vlv_enable_pll()
1746 if (crtc_state->dpll_hw_state.dpll & DPLL_VCO_ENABLE) { in vlv_enable_pll()
1767 bestn = crtc_state->dpll.n; in chv_prepare_pll()
1768 bestm2_frac = crtc_state->dpll.m2 & 0x3fffff; in chv_prepare_pll()
1769 bestm1 = crtc_state->dpll.m1; in chv_prepare_pll()
1770 bestm2 = crtc_state->dpll.m2 >> 22; in chv_prepare_pll()
1771 bestp1 = crtc_state->dpll.p1; in chv_prepare_pll()
1772 bestp2 = crtc_state->dpll.p2; in chv_prepare_pll()
1773 vco = crtc_state->dpll.vco; in chv_prepare_pll()
1875 intel_de_write(dev_priv, DPLL(pipe), crtc_state->dpll_hw_state.dpll); in _chv_enable_pll()
1895 crtc_state->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); in chv_enable_pll()
1897 if (crtc_state->dpll_hw_state.dpll & DPLL_VCO_ENABLE) { in chv_enable_pll()
1940 const struct dpll *dpll) in vlv_force_pll_on() argument
1951 crtc_state->dpll = *dpll; in vlv_force_pll_on()