Lines Matching refs:cfgcr2
1207 i915_reg_t ctl, cfgcr1, cfgcr2; member
1221 .cfgcr2 = DPLL_CFGCR2(SKL_DPLL1),
1227 .cfgcr2 = DPLL_CFGCR2(SKL_DPLL2),
1233 .cfgcr2 = DPLL_CFGCR2(SKL_DPLL3),
1263 intel_de_write(dev_priv, regs[id].cfgcr2, pll->state.hw_state.cfgcr2); in skl_ddi_pll_enable()
1265 intel_de_posting_read(dev_priv, regs[id].cfgcr2); in skl_ddi_pll_enable()
1325 hw_state->cfgcr2 = intel_de_read(dev_priv, regs[id].cfgcr2); in skl_ddi_pll_get_hw_state()
1614 p0 = pll_state->cfgcr2 & DPLL_CFGCR2_PDIV_MASK; in skl_ddi_wrpll_get_freq()
1615 p2 = pll_state->cfgcr2 & DPLL_CFGCR2_KDIV_MASK; in skl_ddi_wrpll_get_freq()
1617 if (pll_state->cfgcr2 & DPLL_CFGCR2_QDIV_MODE(1)) in skl_ddi_wrpll_get_freq()
1618 p1 = (pll_state->cfgcr2 & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8; in skl_ddi_wrpll_get_freq()
1682 u32 ctrl1, cfgcr1, cfgcr2; in skl_ddi_hdmi_pll_dividers() local
1702 cfgcr2 = DPLL_CFGCR2_QDIV_RATIO(wrpll_params.qdiv_ratio) | in skl_ddi_hdmi_pll_dividers()
1710 crtc_state->dpll_hw_state.cfgcr2 = cfgcr2; in skl_ddi_hdmi_pll_dividers()
1860 hw_state->cfgcr2); in skl_dump_hw_state()