Lines Matching refs:dpll
120 for (i = 0; i < dev_priv->display.dpll.num_shared_dpll; i++) { in intel_atomic_duplicate_dpll_state()
121 struct intel_shared_dpll *pll = &dev_priv->display.dpll.shared_dplls[i]; in intel_atomic_duplicate_dpll_state()
156 return &dev_priv->display.dpll.shared_dplls[id]; in intel_get_shared_dpll_by_id()
230 mutex_lock(&dev_priv->display.dpll.lock); in intel_enable_shared_dpll()
256 mutex_unlock(&dev_priv->display.dpll.lock); in intel_enable_shared_dpll()
279 mutex_lock(&dev_priv->display.dpll.lock); in intel_disable_shared_dpll()
302 mutex_unlock(&dev_priv->display.dpll.lock); in intel_disable_shared_dpll()
321 pll = &dev_priv->display.dpll.shared_dplls[i]; in intel_find_shared_dpll()
431 for (i = 0; i < dev_priv->display.dpll.num_shared_dpll; i++) { in intel_shared_dpll_swap_state()
433 &dev_priv->display.dpll.shared_dplls[i]; in intel_shared_dpll_swap_state()
453 hw_state->dpll = val; in ibx_pch_dpll_get_hw_state()
486 intel_de_write(dev_priv, PCH_DPLL(id), pll->state.hw_state.dpll); in ibx_pch_dpll_enable()
497 intel_de_write(dev_priv, PCH_DPLL(id), pll->state.hw_state.dpll); in ibx_pch_dpll_enable()
532 pll = &dev_priv->display.dpll.shared_dplls[i]; in ibx_get_dpll()
563 hw_state->dpll, in ibx_dump_hw_state()
621 if (dev_priv->display.dpll.pch_ssc_use & BIT(id)) in hsw_ddi_wrpll_disable()
639 if (dev_priv->display.dpll.pch_ssc_use & BIT(id)) in hsw_ddi_spll_disable()
902 refclk = dev_priv->display.dpll.ref_clks.nssc; in hsw_ddi_wrpll_get_freq()
912 refclk = dev_priv->display.dpll.ref_clks.ssc; in hsw_ddi_wrpll_get_freq()
1134 i915->display.dpll.ref_clks.ssc = 135000; in hsw_update_dpll_ref_clks()
1137 i915->display.dpll.ref_clks.nssc = 24000; in hsw_update_dpll_ref_clks()
1139 i915->display.dpll.ref_clks.nssc = 135000; in hsw_update_dpll_ref_clks()
1611 int ref_clock = i915->display.dpll.ref_clks.nssc; in skl_ddi_wrpll_get_freq()
1694 i915->display.dpll.ref_clks.nssc, &wrpll_params); in skl_ddi_hdmi_pll_dividers()
1850 i915->display.dpll.ref_clks.nssc = i915->display.cdclk.hw.ref; in skl_update_dpll_ref_clks()
2119 static const struct dpll bxt_dp_clk_val[] = {
2132 struct dpll *clk_div) in bxt_ddi_hdmi_pll_dividers()
2150 struct dpll *clk_div) in bxt_ddi_dp_pll_dividers()
2163 chv_calc_dpll_params(i915->display.dpll.ref_clks.nssc, clk_div); in bxt_ddi_dp_pll_dividers()
2170 const struct dpll *clk_div) in bxt_ddi_set_dpll_hw_state()
2241 struct dpll clock; in bxt_ddi_pll_get_freq()
2251 return chv_calc_dpll_params(i915->display.dpll.ref_clks.nssc, &clock); in bxt_ddi_pll_get_freq()
2257 struct dpll clk_div = {}; in bxt_ddi_dp_set_dpll_hw_state()
2268 struct dpll clk_div = {}; in bxt_ddi_hdmi_set_dpll_hw_state()
2325 i915->display.dpll.ref_clks.ssc = 100000; in bxt_update_dpll_ref_clks()
2326 i915->display.dpll.ref_clks.nssc = 100000; in bxt_update_dpll_ref_clks()
2469 i915->display.dpll.ref_clks.nssc == 38400; in ehl_combo_pll_div_frac_wa_needed()
2563 dev_priv->display.dpll.ref_clks.nssc == 24000 ? in icl_calc_dp_combo_pll()
2586 switch (dev_priv->display.dpll.ref_clks.nssc) { in icl_calc_tbt_pll()
2588 MISSING_CASE(dev_priv->display.dpll.ref_clks.nssc); in icl_calc_tbt_pll()
2599 switch (dev_priv->display.dpll.ref_clks.nssc) { in icl_calc_tbt_pll()
2601 MISSING_CASE(dev_priv->display.dpll.ref_clks.nssc); in icl_calc_tbt_pll()
2631 int ref_clock = i915->display.dpll.ref_clks.nssc; in icl_wrpll_ref_clock()
2858 int refclk_khz = dev_priv->display.dpll.ref_clks.nssc; in icl_calc_mg_pll_state()
3064 ref_clock = dev_priv->display.dpll.ref_clks.nssc; in icl_ddi_mg_pll_get_freq()
3445 if (dev_priv->display.dpll.ref_clks.nssc == 38400) { in mg_pll_get_hw_state()
3966 i915->display.dpll.ref_clks.nssc = i915->display.cdclk.hw.ref; in icl_update_dpll_ref_clks()
4164 mutex_init(&dev_priv->display.dpll.lock); in intel_shared_dpll_init()
4193 dev_priv->display.dpll.num_shared_dpll = 0; in intel_shared_dpll_init()
4201 i >= ARRAY_SIZE(dev_priv->display.dpll.shared_dplls))) in intel_shared_dpll_init()
4205 dev_priv->display.dpll.shared_dplls[i].info = &dpll_info[i]; in intel_shared_dpll_init()
4208 dev_priv->display.dpll.mgr = dpll_mgr; in intel_shared_dpll_init()
4209 dev_priv->display.dpll.num_shared_dpll = i; in intel_shared_dpll_init()
4231 const struct intel_dpll_mgr *dpll_mgr = dev_priv->display.dpll.mgr; in intel_compute_shared_dplls()
4264 const struct intel_dpll_mgr *dpll_mgr = dev_priv->display.dpll.mgr; in intel_reserve_shared_dplls()
4287 const struct intel_dpll_mgr *dpll_mgr = dev_priv->display.dpll.mgr; in intel_release_shared_dplls()
4316 const struct intel_dpll_mgr *dpll_mgr = dev_priv->display.dpll.mgr; in intel_update_active_dpll()
4387 if (i915->display.dpll.mgr && i915->display.dpll.mgr->update_ref_clks) in intel_dpll_update_ref_clks()
4388 i915->display.dpll.mgr->update_ref_clks(i915); in intel_dpll_update_ref_clks()
4395 for (i = 0; i < i915->display.dpll.num_shared_dpll; i++) in intel_dpll_readout_hw_state()
4396 readout_dpll_hw_state(i915, &i915->display.dpll.shared_dplls[i]); in intel_dpll_readout_hw_state()
4422 for (i = 0; i < i915->display.dpll.num_shared_dpll; i++) in intel_dpll_sanitize_state()
4423 sanitize_dpll_state(i915, &i915->display.dpll.shared_dplls[i]); in intel_dpll_sanitize_state()
4436 if (dev_priv->display.dpll.mgr) { in intel_dpll_dump_hw_state()
4437 dev_priv->display.dpll.mgr->dump_hw_state(dev_priv, hw_state); in intel_dpll_dump_hw_state()
4445 hw_state->dpll, in intel_dpll_dump_hw_state()
4535 for (i = 0; i < i915->display.dpll.num_shared_dpll; i++) in intel_shared_dpll_verify_disabled()
4536 verify_single_dpll_state(i915, &i915->display.dpll.shared_dplls[i], in intel_shared_dpll_verify_disabled()