Lines Matching refs:crtc_state
200 const struct intel_crtc_state *crtc_state, in g4x_write_infoframe() argument
236 const struct intel_crtc_state *crtc_state, in g4x_read_infoframe() argument
272 const struct intel_crtc_state *crtc_state, in ibx_write_infoframe() argument
278 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in ibx_write_infoframe()
311 const struct intel_crtc_state *crtc_state, in ibx_read_infoframe() argument
316 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in ibx_read_infoframe()
351 const struct intel_crtc_state *crtc_state, in cpt_write_infoframe() argument
357 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in cpt_write_infoframe()
393 const struct intel_crtc_state *crtc_state, in cpt_read_infoframe() argument
398 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in cpt_read_infoframe()
429 const struct intel_crtc_state *crtc_state, in vlv_write_infoframe() argument
435 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in vlv_write_infoframe()
469 const struct intel_crtc_state *crtc_state, in vlv_read_infoframe() argument
474 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in vlv_read_infoframe()
509 const struct intel_crtc_state *crtc_state, in hsw_write_infoframe() argument
515 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; in hsw_write_infoframe()
541 if (IS_DISPLAY_VER(dev_priv, 13, 14) && crtc_state->has_psr && type == DP_SDP_VSC) in hsw_write_infoframe()
550 const struct intel_crtc_state *crtc_state, in hsw_read_infoframe() argument
554 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; in hsw_read_infoframe()
604 const struct intel_crtc_state *crtc_state) in intel_hdmi_infoframes_enabled() argument
611 val = dig_port->infoframes_enabled(encoder, crtc_state); in intel_hdmi_infoframes_enabled()
647 const struct intel_crtc_state *crtc_state, in intel_write_infoframe() argument
655 if ((crtc_state->infoframes.enable & in intel_write_infoframe()
672 dig_port->write_infoframe(encoder, crtc_state, type, buffer, len); in intel_write_infoframe()
676 const struct intel_crtc_state *crtc_state, in intel_read_infoframe() argument
684 if ((crtc_state->infoframes.enable & in intel_read_infoframe()
688 dig_port->read_infoframe(encoder, crtc_state, in intel_read_infoframe()
710 struct intel_crtc_state *crtc_state, in intel_hdmi_compute_avi_infoframe() argument
713 struct hdmi_avi_infoframe *frame = &crtc_state->infoframes.avi.avi; in intel_hdmi_compute_avi_infoframe()
715 &crtc_state->hw.adjusted_mode; in intel_hdmi_compute_avi_infoframe()
719 if (!crtc_state->has_infoframe) in intel_hdmi_compute_avi_infoframe()
722 crtc_state->infoframes.enable |= in intel_hdmi_compute_avi_infoframe()
730 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) in intel_hdmi_compute_avi_infoframe()
732 else if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) in intel_hdmi_compute_avi_infoframe()
740 drm_WARN_ON(encoder->base.dev, crtc_state->limited_color_range && in intel_hdmi_compute_avi_infoframe()
741 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); in intel_hdmi_compute_avi_infoframe()
743 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB) { in intel_hdmi_compute_avi_infoframe()
746 crtc_state->limited_color_range ? in intel_hdmi_compute_avi_infoframe()
767 struct intel_crtc_state *crtc_state, in intel_hdmi_compute_spd_infoframe() argument
771 struct hdmi_spd_infoframe *frame = &crtc_state->infoframes.spd.spd; in intel_hdmi_compute_spd_infoframe()
774 if (!crtc_state->has_infoframe) in intel_hdmi_compute_spd_infoframe()
777 crtc_state->infoframes.enable |= in intel_hdmi_compute_spd_infoframe()
799 struct intel_crtc_state *crtc_state, in intel_hdmi_compute_hdmi_infoframe() argument
803 &crtc_state->infoframes.hdmi.vendor.hdmi; in intel_hdmi_compute_hdmi_infoframe()
808 if (!crtc_state->has_infoframe || !info->has_hdmi_infoframe) in intel_hdmi_compute_hdmi_infoframe()
811 crtc_state->infoframes.enable |= in intel_hdmi_compute_hdmi_infoframe()
816 &crtc_state->hw.adjusted_mode); in intel_hdmi_compute_hdmi_infoframe()
829 struct intel_crtc_state *crtc_state, in intel_hdmi_compute_drm_infoframe() argument
832 struct hdmi_drm_infoframe *frame = &crtc_state->infoframes.drm.drm; in intel_hdmi_compute_drm_infoframe()
839 if (!crtc_state->has_infoframe) in intel_hdmi_compute_drm_infoframe()
845 crtc_state->infoframes.enable |= in intel_hdmi_compute_drm_infoframe()
864 const struct intel_crtc_state *crtc_state, in g4x_set_infoframes() argument
921 intel_write_infoframe(encoder, crtc_state, in g4x_set_infoframes()
923 &crtc_state->infoframes.avi); in g4x_set_infoframes()
924 intel_write_infoframe(encoder, crtc_state, in g4x_set_infoframes()
926 &crtc_state->infoframes.spd); in g4x_set_infoframes()
927 intel_write_infoframe(encoder, crtc_state, in g4x_set_infoframes()
929 &crtc_state->infoframes.hdmi); in g4x_set_infoframes()
976 const struct intel_crtc_state *crtc_state, in intel_hdmi_set_gcp_infoframe() argument
980 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_hdmi_set_gcp_infoframe()
983 if ((crtc_state->infoframes.enable & in intel_hdmi_set_gcp_infoframe()
988 reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder); in intel_hdmi_set_gcp_infoframe()
996 intel_de_write(dev_priv, reg, crtc_state->infoframes.gcp); in intel_hdmi_set_gcp_infoframe()
1002 struct intel_crtc_state *crtc_state) in intel_hdmi_read_gcp_infoframe() argument
1005 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_hdmi_read_gcp_infoframe()
1008 if ((crtc_state->infoframes.enable & in intel_hdmi_read_gcp_infoframe()
1013 reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder); in intel_hdmi_read_gcp_infoframe()
1021 crtc_state->infoframes.gcp = intel_de_read(dev_priv, reg); in intel_hdmi_read_gcp_infoframe()
1025 struct intel_crtc_state *crtc_state, in intel_hdmi_compute_gcp_infoframe() argument
1030 if (IS_G4X(dev_priv) || !crtc_state->has_infoframe) in intel_hdmi_compute_gcp_infoframe()
1033 crtc_state->infoframes.enable |= in intel_hdmi_compute_gcp_infoframe()
1037 if (crtc_state->pipe_bpp > 24) in intel_hdmi_compute_gcp_infoframe()
1038 crtc_state->infoframes.gcp |= GCP_COLOR_INDICATION; in intel_hdmi_compute_gcp_infoframe()
1041 if (gcp_default_phase_possible(crtc_state->pipe_bpp, in intel_hdmi_compute_gcp_infoframe()
1042 &crtc_state->hw.adjusted_mode)) in intel_hdmi_compute_gcp_infoframe()
1043 crtc_state->infoframes.gcp |= GCP_DEFAULT_PHASE_ENABLE; in intel_hdmi_compute_gcp_infoframe()
1048 const struct intel_crtc_state *crtc_state, in ibx_set_infoframes() argument
1052 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in ibx_set_infoframes()
1088 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) in ibx_set_infoframes()
1094 intel_write_infoframe(encoder, crtc_state, in ibx_set_infoframes()
1096 &crtc_state->infoframes.avi); in ibx_set_infoframes()
1097 intel_write_infoframe(encoder, crtc_state, in ibx_set_infoframes()
1099 &crtc_state->infoframes.spd); in ibx_set_infoframes()
1100 intel_write_infoframe(encoder, crtc_state, in ibx_set_infoframes()
1102 &crtc_state->infoframes.hdmi); in ibx_set_infoframes()
1107 const struct intel_crtc_state *crtc_state, in cpt_set_infoframes() argument
1111 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in cpt_set_infoframes()
1137 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) in cpt_set_infoframes()
1143 intel_write_infoframe(encoder, crtc_state, in cpt_set_infoframes()
1145 &crtc_state->infoframes.avi); in cpt_set_infoframes()
1146 intel_write_infoframe(encoder, crtc_state, in cpt_set_infoframes()
1148 &crtc_state->infoframes.spd); in cpt_set_infoframes()
1149 intel_write_infoframe(encoder, crtc_state, in cpt_set_infoframes()
1151 &crtc_state->infoframes.hdmi); in cpt_set_infoframes()
1156 const struct intel_crtc_state *crtc_state, in vlv_set_infoframes() argument
1160 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in vlv_set_infoframes()
1195 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) in vlv_set_infoframes()
1201 intel_write_infoframe(encoder, crtc_state, in vlv_set_infoframes()
1203 &crtc_state->infoframes.avi); in vlv_set_infoframes()
1204 intel_write_infoframe(encoder, crtc_state, in vlv_set_infoframes()
1206 &crtc_state->infoframes.spd); in vlv_set_infoframes()
1207 intel_write_infoframe(encoder, crtc_state, in vlv_set_infoframes()
1209 &crtc_state->infoframes.hdmi); in vlv_set_infoframes()
1214 const struct intel_crtc_state *crtc_state, in hsw_set_infoframes() argument
1218 i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder); in hsw_set_infoframes()
1222 crtc_state->cpu_transcoder); in hsw_set_infoframes()
1235 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) in hsw_set_infoframes()
1241 intel_write_infoframe(encoder, crtc_state, in hsw_set_infoframes()
1243 &crtc_state->infoframes.avi); in hsw_set_infoframes()
1244 intel_write_infoframe(encoder, crtc_state, in hsw_set_infoframes()
1246 &crtc_state->infoframes.spd); in hsw_set_infoframes()
1247 intel_write_infoframe(encoder, crtc_state, in hsw_set_infoframes()
1249 &crtc_state->infoframes.hdmi); in hsw_set_infoframes()
1250 intel_write_infoframe(encoder, crtc_state, in hsw_set_infoframes()
1252 &crtc_state->infoframes.drm); in hsw_set_infoframes()
1812 static bool intel_hdmi_is_ycbcr420(const struct intel_crtc_state *crtc_state) in intel_hdmi_is_ycbcr420() argument
1814 return crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420; in intel_hdmi_is_ycbcr420()
2034 bool intel_hdmi_bpc_possible(const struct intel_crtc_state *crtc_state, in intel_hdmi_bpc_possible() argument
2037 struct drm_atomic_state *state = crtc_state->uapi.state; in intel_hdmi_bpc_possible()
2043 if (connector_state->crtc != crtc_state->uapi.crtc) in intel_hdmi_bpc_possible()
2053 static bool hdmi_bpc_possible(const struct intel_crtc_state *crtc_state, int bpc) in hdmi_bpc_possible() argument
2056 to_i915(crtc_state->uapi.crtc->dev); in hdmi_bpc_possible()
2058 &crtc_state->hw.adjusted_mode; in hdmi_bpc_possible()
2064 if (intel_hdmi_is_ycbcr420(crtc_state) && in hdmi_bpc_possible()
2070 return intel_hdmi_bpc_possible(crtc_state, bpc, crtc_state->has_hdmi_sink, in hdmi_bpc_possible()
2071 intel_hdmi_is_ycbcr420(crtc_state)); in hdmi_bpc_possible()
2075 struct intel_crtc_state *crtc_state, in intel_hdmi_compute_bpc() argument
2079 bool ycbcr420_output = intel_hdmi_is_ycbcr420(crtc_state); in intel_hdmi_compute_bpc()
2086 bpc = max(crtc_state->pipe_bpp / 3, 8); in intel_hdmi_compute_bpc()
2099 if (hdmi_bpc_possible(crtc_state, bpc) && in intel_hdmi_compute_bpc()
2102 crtc_state->has_hdmi_sink) == MODE_OK) in intel_hdmi_compute_bpc()
2110 struct intel_crtc_state *crtc_state, in intel_hdmi_compute_clock() argument
2115 &crtc_state->hw.adjusted_mode; in intel_hdmi_compute_clock()
2121 bpc = intel_hdmi_compute_bpc(encoder, crtc_state, clock, in intel_hdmi_compute_clock()
2126 crtc_state->port_clock = in intel_hdmi_compute_clock()
2127 intel_hdmi_tmds_clock(clock, bpc, intel_hdmi_is_ycbcr420(crtc_state)); in intel_hdmi_compute_clock()
2134 crtc_state->pipe_bpp = min(crtc_state->pipe_bpp, bpc * 3); in intel_hdmi_compute_clock()
2138 bpc, crtc_state->pipe_bpp); in intel_hdmi_compute_clock()
2143 bool intel_hdmi_limited_color_range(const struct intel_crtc_state *crtc_state, in intel_hdmi_limited_color_range() argument
2149 &crtc_state->hw.adjusted_mode; in intel_hdmi_limited_color_range()
2158 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) in intel_hdmi_limited_color_range()
2163 return crtc_state->has_hdmi_sink && in intel_hdmi_limited_color_range()
2172 const struct intel_crtc_state *crtc_state, in intel_hdmi_has_audio() argument
2179 if (!crtc_state->has_hdmi_sink) in intel_hdmi_has_audio()
2189 intel_hdmi_output_format(const struct intel_crtc_state *crtc_state, in intel_hdmi_output_format() argument
2193 if (!crtc_state->has_hdmi_sink) in intel_hdmi_output_format()
2203 struct intel_crtc_state *crtc_state, in intel_hdmi_compute_output_format() argument
2208 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; in intel_hdmi_compute_output_format()
2214 crtc_state->output_format = in intel_hdmi_compute_output_format()
2215 intel_hdmi_output_format(crtc_state, connector, ycbcr_420_only); in intel_hdmi_compute_output_format()
2217 if (ycbcr_420_only && !intel_hdmi_is_ycbcr420(crtc_state)) { in intel_hdmi_compute_output_format()
2220 crtc_state->output_format = INTEL_OUTPUT_FORMAT_RGB; in intel_hdmi_compute_output_format()
2223 ret = intel_hdmi_compute_clock(encoder, crtc_state, respect_downstream_limits); in intel_hdmi_compute_output_format()
2225 if (intel_hdmi_is_ycbcr420(crtc_state) || in intel_hdmi_compute_output_format()
2230 crtc_state->output_format = intel_hdmi_output_format(crtc_state, connector, true); in intel_hdmi_compute_output_format()
2231 ret = intel_hdmi_compute_clock(encoder, crtc_state, respect_downstream_limits); in intel_hdmi_compute_output_format()
2237 static bool intel_hdmi_is_cloned(const struct intel_crtc_state *crtc_state) in intel_hdmi_is_cloned() argument
2239 return crtc_state->uapi.encoder_mask && in intel_hdmi_is_cloned()
2240 !is_power_of_2(crtc_state->uapi.encoder_mask); in intel_hdmi_is_cloned()
3050 intel_hdmi_dsc_get_num_slices(const struct intel_crtc_state *crtc_state, in intel_hdmi_dsc_get_num_slices() argument
3072 int pixel_clock = crtc_state->hw.adjusted_mode.crtc_clock; in intel_hdmi_dsc_get_num_slices()
3083 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 || in intel_hdmi_dsc_get_num_slices()
3084 crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB) in intel_hdmi_dsc_get_num_slices()
3139 slice_width = DIV_ROUND_UP(crtc_state->hw.adjusted_mode.hdisplay, target_slices); in intel_hdmi_dsc_get_num_slices()