Lines Matching refs:crtc_state
692 struct intel_crtc_state *crtc_state) in dc3co_is_pipe_port_compatible() argument
695 enum pipe pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe; in dc3co_is_pipe_port_compatible()
707 struct intel_crtc_state *crtc_state) in tgl_dc3co_exitline_compute_config() argument
709 const u32 crtc_vdisplay = crtc_state->uapi.adjusted_mode.crtc_vdisplay; in tgl_dc3co_exitline_compute_config()
724 if (crtc_state->enable_psr2_sel_fetch) in tgl_dc3co_exitline_compute_config()
730 if (!dc3co_is_pipe_port_compatible(intel_dp, crtc_state)) in tgl_dc3co_exitline_compute_config()
742 intel_usecs_to_scanlines(&crtc_state->uapi.adjusted_mode, 200) + 1; in tgl_dc3co_exitline_compute_config()
747 crtc_state->dc3co_exitline = crtc_vdisplay - exit_scanlines; in tgl_dc3co_exitline_compute_config()
751 struct intel_crtc_state *crtc_state) in intel_psr2_sel_fetch_config_valid() argument
762 if (crtc_state->uapi.async_flip) { in intel_psr2_sel_fetch_config_valid()
775 return crtc_state->enable_psr2_sel_fetch = true; in intel_psr2_sel_fetch_config_valid()
779 struct intel_crtc_state *crtc_state) in psr2_granularity_check() argument
782 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; in psr2_granularity_check()
783 const int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay; in psr2_granularity_check()
784 const int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay; in psr2_granularity_check()
795 if (!crtc_state->enable_psr2_sel_fetch) in psr2_granularity_check()
813 if (crtc_state->dsc.compression_enable && in psr2_granularity_check()
817 crtc_state->su_y_granularity = y_granularity; in psr2_granularity_check()
822 struct intel_crtc_state *crtc_state) in _compute_psr2_sdp_prior_scanline_indication() argument
824 const struct drm_display_mode *adjusted_mode = &crtc_state->uapi.adjusted_mode; in _compute_psr2_sdp_prior_scanline_indication()
832 req_ns = ((60 / crtc_state->lane_count) + 11) * 1000 / (crtc_state->port_clock / 1000); in _compute_psr2_sdp_prior_scanline_indication()
841 crtc_state->req_psr2_sdp_prior_scanline = true; in _compute_psr2_sdp_prior_scanline_indication()
846 struct intel_crtc_state *crtc_state) in intel_psr2_config_valid() argument
849 int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay; in intel_psr2_config_valid()
850 int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay; in intel_psr2_config_valid()
874 if (!transcoder_has_psr2(dev_priv, crtc_state->cpu_transcoder)) { in intel_psr2_config_valid()
877 transcoder_name(crtc_state->cpu_transcoder)); in intel_psr2_config_valid()
891 if (crtc_state->dsc.compression_enable && in intel_psr2_config_valid()
898 if (crtc_state->crc_enabled) { in intel_psr2_config_valid()
918 if (crtc_state->pipe_bpp > max_bpp) { in intel_psr2_config_valid()
921 crtc_state->pipe_bpp, max_bpp); in intel_psr2_config_valid()
926 if (crtc_state->vrr.enable && in intel_psr2_config_valid()
933 if (!_compute_psr2_sdp_prior_scanline_indication(intel_dp, crtc_state)) { in intel_psr2_config_valid()
940 if (!intel_psr2_sel_fetch_config_valid(intel_dp, crtc_state) && in intel_psr2_config_valid()
949 if (!crtc_state->enable_psr2_sel_fetch && in intel_psr2_config_valid()
955 if (!psr2_granularity_check(intel_dp, crtc_state)) { in intel_psr2_config_valid()
960 if (!crtc_state->enable_psr2_sel_fetch && in intel_psr2_config_valid()
969 tgl_dc3co_exitline_compute_config(intel_dp, crtc_state); in intel_psr2_config_valid()
973 crtc_state->enable_psr2_sel_fetch = false; in intel_psr2_config_valid()
978 struct intel_crtc_state *crtc_state, in intel_psr_compute_config() argument
983 &crtc_state->hw.adjusted_mode; in intel_psr_compute_config()
990 if (crtc_state->vrr.enable) in intel_psr_compute_config()
1029 crtc_state->has_psr = true; in intel_psr_compute_config()
1030 crtc_state->has_psr2 = intel_psr2_config_valid(intel_dp, crtc_state); in intel_psr_compute_config()
1032 crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC); in intel_psr_compute_config()
1033 intel_dp_compute_psr_vsc_sdp(intel_dp, crtc_state, conn_state, in intel_psr_compute_config()
1034 &crtc_state->psr_vsc); in intel_psr_compute_config()
1123 const struct intel_crtc_state *crtc_state) in intel_psr_enable_source() argument
1175 vtotal = crtc_state->uapi.adjusted_mode.crtc_vtotal - in intel_psr_enable_source()
1176 crtc_state->uapi.adjusted_mode.crtc_vdisplay; in intel_psr_enable_source()
1177 vblank = crtc_state->uapi.adjusted_mode.crtc_vblank_end - in intel_psr_enable_source()
1178 crtc_state->uapi.adjusted_mode.crtc_vblank_start; in intel_psr_enable_source()
1250 const struct intel_crtc_state *crtc_state) in intel_psr_enable_locked() argument
1260 intel_dp->psr.psr2_enabled = crtc_state->has_psr2; in intel_psr_enable_locked()
1262 intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe; in intel_psr_enable_locked()
1263 intel_dp->psr.transcoder = crtc_state->cpu_transcoder; in intel_psr_enable_locked()
1265 val = usecs_to_jiffies(intel_get_frame_time_us(crtc_state) * 6); in intel_psr_enable_locked()
1267 intel_dp->psr.dc3co_exitline = crtc_state->dc3co_exitline; in intel_psr_enable_locked()
1268 intel_dp->psr.psr2_sel_fetch_enabled = crtc_state->enable_psr2_sel_fetch; in intel_psr_enable_locked()
1271 crtc_state->req_psr2_sdp_prior_scanline; in intel_psr_enable_locked()
1278 intel_write_dp_vsc_sdp(encoder, crtc_state, &crtc_state->psr_vsc); in intel_psr_enable_locked()
1281 intel_psr_enable_source(intel_dp, crtc_state); in intel_psr_enable_locked()
1551 const struct intel_crtc_state *crtc_state) in intel_psr2_disable_plane_sel_fetch() argument
1556 if (!crtc_state->enable_psr2_sel_fetch) in intel_psr2_disable_plane_sel_fetch()
1563 const struct intel_crtc_state *crtc_state, in intel_psr2_program_plane_sel_fetch() argument
1573 if (!crtc_state->enable_psr2_sel_fetch) in intel_psr2_program_plane_sel_fetch()
1613 void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state *crtc_state) in intel_psr2_program_trans_man_trk_ctl() argument
1615 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); in intel_psr2_program_trans_man_trk_ctl()
1618 if (!crtc_state->enable_psr2_sel_fetch) in intel_psr2_program_trans_man_trk_ctl()
1622 crtc_state->uapi.encoder_mask) { in intel_psr2_program_trans_man_trk_ctl()
1631 intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(crtc_state->cpu_transcoder), in intel_psr2_program_trans_man_trk_ctl()
1632 crtc_state->psr2_man_track_ctl); in intel_psr2_program_trans_man_trk_ctl()
1635 static void psr2_man_trk_ctl_calc(struct intel_crtc_state *crtc_state, in psr2_man_trk_ctl_calc() argument
1638 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in psr2_man_trk_ctl_calc()
1658 drm_WARN_ON(crtc_state->uapi.crtc->dev, clip->y1 % 4 || clip->y2 % 4); in psr2_man_trk_ctl_calc()
1664 crtc_state->psr2_man_track_ctl = val; in psr2_man_trk_ctl_calc()
1687 static void intel_psr2_sel_fetch_pipe_alignment(const struct intel_crtc_state *crtc_state, in intel_psr2_sel_fetch_pipe_alignment() argument
1690 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); in intel_psr2_sel_fetch_pipe_alignment()
1691 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; in intel_psr2_sel_fetch_pipe_alignment()
1695 if (crtc_state->dsc.compression_enable && in intel_psr2_sel_fetch_pipe_alignment()
1699 y_alignment = crtc_state->su_y_granularity; in intel_psr2_sel_fetch_pipe_alignment()
1733 static bool psr2_sel_fetch_pipe_state_supported(const struct intel_crtc_state *crtc_state) in psr2_sel_fetch_pipe_state_supported() argument
1735 if (crtc_state->scaler_state.scaler_id >= 0) in psr2_sel_fetch_pipe_state_supported()
1745 struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); in intel_psr2_sel_fetch_update() local
1752 if (!crtc_state->enable_psr2_sel_fetch) in intel_psr2_sel_fetch_update()
1755 if (!psr2_sel_fetch_pipe_state_supported(crtc_state)) { in intel_psr2_sel_fetch_update()
1771 if (new_plane_state->uapi.crtc != crtc_state->uapi.crtc) in intel_psr2_sel_fetch_update()
1795 &crtc_state->pipe_src); in intel_psr2_sel_fetch_update()
1802 &crtc_state->pipe_src); in intel_psr2_sel_fetch_update()
1810 &crtc_state->pipe_src); in intel_psr2_sel_fetch_update()
1826 clip_area_update(&pipe_clip, &damaged_area, &crtc_state->pipe_src); in intel_psr2_sel_fetch_update()
1848 crtc_state->splitter.enable) in intel_psr2_sel_fetch_update()
1855 intel_psr2_sel_fetch_pipe_alignment(crtc_state, &pipe_clip); in intel_psr2_sel_fetch_update()
1866 if (new_plane_state->uapi.crtc != crtc_state->uapi.crtc || in intel_psr2_sel_fetch_update()
1882 crtc_state->update_planes |= BIT(plane->id); in intel_psr2_sel_fetch_update()
1899 crtc_state->update_planes |= BIT(linked->id); in intel_psr2_sel_fetch_update()
1904 psr2_man_trk_ctl_calc(crtc_state, &pipe_clip, full_update); in intel_psr2_sel_fetch_update()
1948 const struct intel_crtc_state *crtc_state) in _intel_psr_post_plane_update() argument
1953 if (!crtc_state->has_psr) in _intel_psr_post_plane_update()
1957 crtc_state->uapi.encoder_mask) { in _intel_psr_post_plane_update()
1966 drm_WARN_ON(&dev_priv->drm, psr->enabled && !crtc_state->active_planes); in _intel_psr_post_plane_update()
1969 if (!psr->enabled && crtc_state->active_planes) in _intel_psr_post_plane_update()
1970 intel_psr_enable_locked(intel_dp, crtc_state); in _intel_psr_post_plane_update()
1973 if (crtc_state->crc_enabled && psr->enabled) in _intel_psr_post_plane_update()
1984 struct intel_crtc_state *crtc_state; in intel_psr_post_plane_update() local
1991 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) in intel_psr_post_plane_update()
1992 _intel_psr_post_plane_update(state, crtc_state); in intel_psr_post_plane_update()
2109 struct drm_crtc_state *crtc_state; in intel_psr_fastset_force() local
2123 crtc_state = drm_atomic_get_crtc_state(state, conn_state->crtc); in intel_psr_fastset_force()
2124 if (IS_ERR(crtc_state)) { in intel_psr_fastset_force()
2125 err = PTR_ERR(crtc_state); in intel_psr_fastset_force()
2130 crtc_state->mode_changed = true; in intel_psr_fastset_force()
2611 void intel_psr_lock(const struct intel_crtc_state *crtc_state) in intel_psr_lock() argument
2613 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); in intel_psr_lock()
2616 if (!crtc_state->has_psr) in intel_psr_lock()
2620 crtc_state->uapi.encoder_mask) { in intel_psr_lock()
2634 void intel_psr_unlock(const struct intel_crtc_state *crtc_state) in intel_psr_unlock() argument
2636 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); in intel_psr_unlock()
2639 if (!crtc_state->has_psr) in intel_psr_unlock()
2643 crtc_state->uapi.encoder_mask) { in intel_psr_unlock()