Lines Matching refs:vdsc_cfg
377 struct drm_dsc_config *vdsc_cfg) in calculate_rc_params() argument
379 int bpc = vdsc_cfg->bits_per_component; in calculate_rc_params()
380 int bpp = vdsc_cfg->bits_per_pixel >> 4; in calculate_rc_params()
396 if (vdsc_cfg->slice_height >= 8) in calculate_rc_params()
398 12 + DIV_ROUND_UP((9 * min(34, vdsc_cfg->slice_height - 8)), 100); in calculate_rc_params()
400 rc->first_line_bpg_offset = 2 * (vdsc_cfg->slice_height - 1); in calculate_rc_params()
454 struct drm_dsc_config *vdsc_cfg = &pipe_config->dsc.config; in intel_dsc_compute_params() local
460 vdsc_cfg->pic_width = pipe_config->hw.adjusted_mode.crtc_hdisplay; in intel_dsc_compute_params()
461 vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width, in intel_dsc_compute_params()
465 vdsc_cfg->simple_422 = false; in intel_dsc_compute_params()
467 vdsc_cfg->vbr_enable = false; in intel_dsc_compute_params()
470 vdsc_cfg->bits_per_pixel = compressed_bpp << 4; in intel_dsc_compute_params()
471 vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3; in intel_dsc_compute_params()
479 vdsc_cfg->rc_buf_thresh[i] = rc_buf_thresh[i] >> 6; in intel_dsc_compute_params()
487 vdsc_cfg->rc_buf_thresh[12] = 0x7C; in intel_dsc_compute_params()
488 vdsc_cfg->rc_buf_thresh[13] = 0x7D; in intel_dsc_compute_params()
501 calculate_rc_params(rc, vdsc_cfg); in intel_dsc_compute_params()
505 vdsc_cfg->bits_per_component); in intel_dsc_compute_params()
510 vdsc_cfg->first_line_bpg_offset = rc_params->first_line_bpg_offset; in intel_dsc_compute_params()
511 vdsc_cfg->initial_xmit_delay = rc_params->initial_xmit_delay; in intel_dsc_compute_params()
512 vdsc_cfg->initial_offset = rc_params->initial_offset; in intel_dsc_compute_params()
513 vdsc_cfg->flatness_min_qp = rc_params->flatness_min_qp; in intel_dsc_compute_params()
514 vdsc_cfg->flatness_max_qp = rc_params->flatness_max_qp; in intel_dsc_compute_params()
515 vdsc_cfg->rc_quant_incr_limit0 = rc_params->rc_quant_incr_limit0; in intel_dsc_compute_params()
516 vdsc_cfg->rc_quant_incr_limit1 = rc_params->rc_quant_incr_limit1; in intel_dsc_compute_params()
519 vdsc_cfg->rc_range_params[i].range_min_qp = in intel_dsc_compute_params()
521 vdsc_cfg->rc_range_params[i].range_max_qp = in intel_dsc_compute_params()
527 vdsc_cfg->rc_range_params[i].range_bpg_offset = in intel_dsc_compute_params()
537 if (vdsc_cfg->bits_per_component <= 10) in intel_dsc_compute_params()
538 vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_8_10_BPC; in intel_dsc_compute_params()
540 vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_12_BPC; in intel_dsc_compute_params()
543 vdsc_cfg->initial_scale_value = (vdsc_cfg->rc_model_size << 3) / in intel_dsc_compute_params()
544 (vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset); in intel_dsc_compute_params()
580 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; in intel_dsc_pps_configure() local
593 pps_val = DSC_VER_MAJ | vdsc_cfg->dsc_version_minor << in intel_dsc_pps_configure()
595 vdsc_cfg->bits_per_component << DSC_BPC_SHIFT | in intel_dsc_pps_configure()
596 vdsc_cfg->line_buf_depth << DSC_LINE_BUF_DEPTH_SHIFT; in intel_dsc_pps_configure()
597 if (vdsc_cfg->dsc_version_minor == 2) in intel_dsc_pps_configure()
599 if (vdsc_cfg->block_pred_enable) in intel_dsc_pps_configure()
601 if (vdsc_cfg->convert_rgb) in intel_dsc_pps_configure()
603 if (vdsc_cfg->simple_422) in intel_dsc_pps_configure()
605 if (vdsc_cfg->vbr_enable) in intel_dsc_pps_configure()
630 pps_val |= DSC_BPP(vdsc_cfg->bits_per_pixel); in intel_dsc_pps_configure()
654 pps_val |= DSC_PIC_HEIGHT(vdsc_cfg->pic_height) | in intel_dsc_pps_configure()
655 DSC_PIC_WIDTH(vdsc_cfg->pic_width / num_vdsc_instances); in intel_dsc_pps_configure()
679 pps_val |= DSC_SLICE_HEIGHT(vdsc_cfg->slice_height) | in intel_dsc_pps_configure()
680 DSC_SLICE_WIDTH(vdsc_cfg->slice_width); in intel_dsc_pps_configure()
704 pps_val |= DSC_INITIAL_XMIT_DELAY(vdsc_cfg->initial_xmit_delay) | in intel_dsc_pps_configure()
705 DSC_INITIAL_DEC_DELAY(vdsc_cfg->initial_dec_delay); in intel_dsc_pps_configure()
729 pps_val |= DSC_SCALE_INC_INT(vdsc_cfg->scale_increment_interval) | in intel_dsc_pps_configure()
730 DSC_SCALE_DEC_INT(vdsc_cfg->scale_decrement_interval); in intel_dsc_pps_configure()
754 pps_val |= DSC_INITIAL_SCALE_VALUE(vdsc_cfg->initial_scale_value) | in intel_dsc_pps_configure()
755 DSC_FIRST_LINE_BPG_OFFSET(vdsc_cfg->first_line_bpg_offset) | in intel_dsc_pps_configure()
756 DSC_FLATNESS_MIN_QP(vdsc_cfg->flatness_min_qp) | in intel_dsc_pps_configure()
757 DSC_FLATNESS_MAX_QP(vdsc_cfg->flatness_max_qp); in intel_dsc_pps_configure()
781 pps_val |= DSC_SLICE_BPG_OFFSET(vdsc_cfg->slice_bpg_offset) | in intel_dsc_pps_configure()
782 DSC_NFL_BPG_OFFSET(vdsc_cfg->nfl_bpg_offset); in intel_dsc_pps_configure()
806 pps_val |= DSC_FINAL_OFFSET(vdsc_cfg->final_offset) | in intel_dsc_pps_configure()
807 DSC_INITIAL_OFFSET(vdsc_cfg->initial_offset); in intel_dsc_pps_configure()
831 pps_val |= DSC_RC_MODEL_SIZE(vdsc_cfg->rc_model_size) | in intel_dsc_pps_configure()
856 pps_val |= DSC_RC_QUANT_INC_LIMIT0(vdsc_cfg->rc_quant_incr_limit0) | in intel_dsc_pps_configure()
857 DSC_RC_QUANT_INC_LIMIT1(vdsc_cfg->rc_quant_incr_limit1) | in intel_dsc_pps_configure()
883 pps_val |= DSC_SLICE_CHUNK_SIZE(vdsc_cfg->slice_chunk_size) | in intel_dsc_pps_configure()
884 DSC_SLICE_PER_LINE((vdsc_cfg->pic_width / num_vdsc_instances) / in intel_dsc_pps_configure()
885 vdsc_cfg->slice_width) | in intel_dsc_pps_configure()
886 DSC_SLICE_ROW_PER_FRAME(vdsc_cfg->pic_height / in intel_dsc_pps_configure()
887 vdsc_cfg->slice_height); in intel_dsc_pps_configure()
913 (u32)(vdsc_cfg->rc_buf_thresh[i] << in intel_dsc_pps_configure()
966 (u32)(((vdsc_cfg->rc_range_params[i].range_bpg_offset << in intel_dsc_pps_configure()
968 (vdsc_cfg->rc_range_params[i].range_max_qp << in intel_dsc_pps_configure()
970 (vdsc_cfg->rc_range_params[i].range_min_qp << in intel_dsc_pps_configure()
1067 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; in intel_dsc_dsi_pps_write() local
1076 drm_dsc_pps_payload_pack(&pps, vdsc_cfg); in intel_dsc_dsi_pps_write()
1090 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; in intel_dsc_dp_pps_write() local
1100 drm_dsc_pps_payload_pack(&dp_dsc_pps_sdp.pps_payload, vdsc_cfg); in intel_dsc_dp_pps_write()
1178 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; in intel_dsc_get_config() local
1212 vdsc_cfg->bits_per_pixel = val; in intel_dsc_get_config()
1213 crtc_state->dsc.compressed_bpp = vdsc_cfg->bits_per_pixel >> 4; in intel_dsc_get_config()