Lines Matching refs:wm
353 const struct skl_plane_wm *wm = in skl_crtc_can_enable_sagv() local
354 &crtc_state->wm.skl.optimal.planes[plane_id]; in skl_crtc_can_enable_sagv()
358 if (!wm->wm[0].enable) in skl_crtc_can_enable_sagv()
363 !wm->wm[level].enable; --level) in skl_crtc_can_enable_sagv()
375 const struct skl_plane_wm *wm = in skl_crtc_can_enable_sagv() local
376 &crtc_state->wm.skl.optimal.planes[plane_id]; in skl_crtc_can_enable_sagv()
382 if (wm->wm[0].enable && !wm->wm[max_level].can_sagv) in skl_crtc_can_enable_sagv()
398 const struct skl_plane_wm *wm = in tgl_crtc_can_enable_sagv() local
399 &crtc_state->wm.skl.optimal.planes[plane_id]; in tgl_crtc_can_enable_sagv()
401 if (wm->wm[0].enable && !wm->sagv.wm0.enable) in tgl_crtc_can_enable_sagv()
478 struct skl_pipe_wm *pipe_wm = &new_crtc_state->wm.skl.optimal; in intel_compute_sagv_mask()
679 crtc_state->wm.skl.ddb.start = mbus_offset + new_dbuf_state->ddb[pipe].start; in skl_crtc_allocate_ddb()
680 crtc_state->wm.skl.ddb.end = mbus_offset + new_dbuf_state->ddb[pipe].end; in skl_crtc_allocate_ddb()
714 struct skl_wm_level wm = {}; in skl_cursor_allocation() local
726 unsigned int latency = i915->display.wm.skl_latency[level]; in skl_cursor_allocation()
728 skl_compute_plane_wm(crtc_state, plane, level, latency, &wp, &wm, &wm); in skl_cursor_allocation()
729 if (wm.min_ddb_alloc == U16_MAX) in skl_cursor_allocation()
732 min_ddb_alloc = wm.min_ddb_alloc; in skl_cursor_allocation()
1360 const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id]; in skl_plane_wm_level() local
1363 return &wm->sagv.wm0; in skl_plane_wm_level()
1365 return &wm->wm[level]; in skl_plane_wm_level()
1372 const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id]; in skl_plane_trans_wm() local
1375 return &wm->sagv.trans_wm; in skl_plane_trans_wm()
1377 return &wm->trans_wm; in skl_plane_trans_wm()
1393 skl_check_wm_level(struct skl_wm_level *wm, const struct skl_ddb_entry *ddb) in skl_check_wm_level() argument
1395 if (wm->min_ddb_alloc > skl_ddb_entry_size(ddb)) in skl_check_wm_level()
1396 memset(wm, 0, sizeof(*wm)); in skl_check_wm_level()
1400 skl_check_nv12_wm_level(struct skl_wm_level *wm, struct skl_wm_level *uv_wm, in skl_check_nv12_wm_level() argument
1403 if (wm->min_ddb_alloc > skl_ddb_entry_size(ddb_y) || in skl_check_nv12_wm_level()
1405 memset(wm, 0, sizeof(*wm)); in skl_check_nv12_wm_level()
1430 const struct skl_wm_level *wm, in skl_allocate_plane_ddb() argument
1448 size = wm->min_ddb_alloc + extra; in skl_allocate_plane_ddb()
1472 memset(crtc_state->wm.skl.plane_ddb, 0, sizeof(crtc_state->wm.skl.plane_ddb)); in skl_crtc_allocate_plane_ddb()
1473 memset(crtc_state->wm.skl.plane_ddb_y, 0, sizeof(crtc_state->wm.skl.plane_ddb_y)); in skl_crtc_allocate_plane_ddb()
1486 skl_ddb_entry_init(&crtc_state->wm.skl.plane_ddb[PLANE_CURSOR], in skl_crtc_allocate_plane_ddb()
1498 const struct skl_plane_wm *wm = in skl_crtc_allocate_plane_ddb() local
1499 &crtc_state->wm.skl.optimal.planes[plane_id]; in skl_crtc_allocate_plane_ddb()
1503 &crtc_state->wm.skl.plane_ddb[plane_id]; in skl_crtc_allocate_plane_ddb()
1505 if (wm->wm[level].min_ddb_alloc > skl_ddb_entry_size(ddb)) { in skl_crtc_allocate_plane_ddb()
1507 wm->wm[level].min_ddb_alloc != U16_MAX); in skl_crtc_allocate_plane_ddb()
1514 blocks += wm->wm[level].min_ddb_alloc; in skl_crtc_allocate_plane_ddb()
1515 blocks += wm->uv_wm[level].min_ddb_alloc; in skl_crtc_allocate_plane_ddb()
1543 &crtc_state->wm.skl.plane_ddb[plane_id]; in skl_crtc_allocate_plane_ddb()
1545 &crtc_state->wm.skl.plane_ddb_y[plane_id]; in skl_crtc_allocate_plane_ddb()
1546 const struct skl_plane_wm *wm = in skl_crtc_allocate_plane_ddb() local
1547 &crtc_state->wm.skl.optimal.planes[plane_id]; in skl_crtc_allocate_plane_ddb()
1554 skl_allocate_plane_ddb(&iter, ddb_y, &wm->wm[level], in skl_crtc_allocate_plane_ddb()
1556 skl_allocate_plane_ddb(&iter, ddb, &wm->uv_wm[level], in skl_crtc_allocate_plane_ddb()
1559 skl_allocate_plane_ddb(&iter, ddb, &wm->wm[level], in skl_crtc_allocate_plane_ddb()
1574 &crtc_state->wm.skl.plane_ddb[plane_id]; in skl_crtc_allocate_plane_ddb()
1576 &crtc_state->wm.skl.plane_ddb_y[plane_id]; in skl_crtc_allocate_plane_ddb()
1577 struct skl_plane_wm *wm = in skl_crtc_allocate_plane_ddb() local
1578 &crtc_state->wm.skl.optimal.planes[plane_id]; in skl_crtc_allocate_plane_ddb()
1582 skl_check_nv12_wm_level(&wm->wm[level], in skl_crtc_allocate_plane_ddb()
1583 &wm->uv_wm[level], in skl_crtc_allocate_plane_ddb()
1586 skl_check_wm_level(&wm->wm[level], ddb); in skl_crtc_allocate_plane_ddb()
1589 level == 1 && !wm->wm[level].enable && in skl_crtc_allocate_plane_ddb()
1590 wm->wm[0].enable) { in skl_crtc_allocate_plane_ddb()
1591 wm->wm[level].blocks = wm->wm[0].blocks; in skl_crtc_allocate_plane_ddb()
1592 wm->wm[level].lines = wm->wm[0].lines; in skl_crtc_allocate_plane_ddb()
1593 wm->wm[level].ignore_lines = wm->wm[0].ignore_lines; in skl_crtc_allocate_plane_ddb()
1604 &crtc_state->wm.skl.plane_ddb[plane_id]; in skl_crtc_allocate_plane_ddb()
1606 &crtc_state->wm.skl.plane_ddb_y[plane_id]; in skl_crtc_allocate_plane_ddb()
1607 struct skl_plane_wm *wm = in skl_crtc_allocate_plane_ddb() local
1608 &crtc_state->wm.skl.optimal.planes[plane_id]; in skl_crtc_allocate_plane_ddb()
1612 skl_check_wm_level(&wm->trans_wm, ddb_y); in skl_crtc_allocate_plane_ddb()
1616 skl_check_wm_level(&wm->trans_wm, ddb); in skl_crtc_allocate_plane_ddb()
1619 skl_check_wm_level(&wm->sagv.wm0, ddb); in skl_crtc_allocate_plane_ddb()
1620 skl_check_wm_level(&wm->sagv.trans_wm, ddb); in skl_crtc_allocate_plane_ddb()
1975 unsigned int latency = i915->display.wm.skl_latency[level]; in skl_compute_wm_levels()
1991 struct skl_wm_level *levels = plane_wm->wm; in tgl_compute_sagv_wm()
1995 latency = i915->display.sagv.block_time_us + i915->display.wm.skl_latency[0]; in tgl_compute_sagv_wm()
2071 struct skl_plane_wm *wm = &crtc_state->wm.skl.raw.planes[plane->id]; in skl_build_plane_wm_single() local
2080 skl_compute_wm_levels(crtc_state, plane, &wm_params, wm->wm); in skl_build_plane_wm_single()
2082 skl_compute_transition_wm(i915, &wm->trans_wm, in skl_build_plane_wm_single()
2083 &wm->wm[0], &wm_params); in skl_build_plane_wm_single()
2086 tgl_compute_sagv_wm(crtc_state, plane, &wm_params, wm); in skl_build_plane_wm_single()
2088 skl_compute_transition_wm(i915, &wm->sagv.trans_wm, in skl_build_plane_wm_single()
2089 &wm->sagv.wm0, &wm_params); in skl_build_plane_wm_single()
2099 struct skl_plane_wm *wm = &crtc_state->wm.skl.raw.planes[plane->id]; in skl_build_plane_wm_uv() local
2103 wm->is_planar = true; in skl_build_plane_wm_uv()
2111 skl_compute_wm_levels(crtc_state, plane, &wm_params, wm->uv_wm); in skl_build_plane_wm_uv()
2121 struct skl_plane_wm *wm = &crtc_state->wm.skl.raw.planes[plane_id]; in skl_build_plane_wm() local
2125 memset(wm, 0, sizeof(*wm)); in skl_build_plane_wm()
2151 struct skl_plane_wm *wm = &crtc_state->wm.skl.raw.planes[plane_id]; in icl_build_plane_wm() local
2158 memset(wm, 0, sizeof(*wm)); in icl_build_plane_wm()
2214 crtc_state->wm.skl.optimal = crtc_state->wm.skl.raw; in skl_build_pipe_wm()
2254 const struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal; in skl_write_plane_wm()
2256 &crtc_state->wm.skl.plane_ddb[plane_id]; in skl_write_plane_wm()
2258 &crtc_state->wm.skl.plane_ddb_y[plane_id]; in skl_write_plane_wm()
2268 const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id]; in skl_write_plane_wm() local
2271 &wm->sagv.wm0); in skl_write_plane_wm()
2273 &wm->sagv.trans_wm); in skl_write_plane_wm()
2291 const struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal; in skl_write_cursor_wm()
2293 &crtc_state->wm.skl.plane_ddb[plane_id]; in skl_write_cursor_wm()
2303 const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id]; in skl_write_cursor_wm() local
2306 &wm->sagv.wm0); in skl_write_cursor_wm()
2308 &wm->sagv.trans_wm); in skl_write_cursor_wm()
2335 if (!skl_wm_level_equals(&wm1->wm[level], &wm2->wm[level])) in skl_plane_wm_equals()
2390 if (skl_ddb_entry_equal(&old_crtc_state->wm.skl.plane_ddb[plane_id], in skl_ddb_add_affected_planes()
2391 &new_crtc_state->wm.skl.plane_ddb[plane_id]) && in skl_ddb_add_affected_planes()
2392 skl_ddb_entry_equal(&old_crtc_state->wm.skl.plane_ddb_y[plane_id], in skl_ddb_add_affected_planes()
2393 &new_crtc_state->wm.skl.plane_ddb_y[plane_id])) in skl_ddb_add_affected_planes()
2555 old_pipe_wm = &old_crtc_state->wm.skl.optimal; in skl_print_wm_changes()
2556 new_pipe_wm = &new_crtc_state->wm.skl.optimal; in skl_print_wm_changes()
2562 old = &old_crtc_state->wm.skl.plane_ddb[plane_id]; in skl_print_wm_changes()
2563 new = &new_crtc_state->wm.skl.plane_ddb[plane_id]; in skl_print_wm_changes()
2589 enast(old_wm->wm[0].enable), enast(old_wm->wm[1].enable), in skl_print_wm_changes()
2590 enast(old_wm->wm[2].enable), enast(old_wm->wm[3].enable), in skl_print_wm_changes()
2591 enast(old_wm->wm[4].enable), enast(old_wm->wm[5].enable), in skl_print_wm_changes()
2592 enast(old_wm->wm[6].enable), enast(old_wm->wm[7].enable), in skl_print_wm_changes()
2596 enast(new_wm->wm[0].enable), enast(new_wm->wm[1].enable), in skl_print_wm_changes()
2597 enast(new_wm->wm[2].enable), enast(new_wm->wm[3].enable), in skl_print_wm_changes()
2598 enast(new_wm->wm[4].enable), enast(new_wm->wm[5].enable), in skl_print_wm_changes()
2599 enast(new_wm->wm[6].enable), enast(new_wm->wm[7].enable), in skl_print_wm_changes()
2608 enast(old_wm->wm[0].ignore_lines), old_wm->wm[0].lines, in skl_print_wm_changes()
2609 enast(old_wm->wm[1].ignore_lines), old_wm->wm[1].lines, in skl_print_wm_changes()
2610 enast(old_wm->wm[2].ignore_lines), old_wm->wm[2].lines, in skl_print_wm_changes()
2611 enast(old_wm->wm[3].ignore_lines), old_wm->wm[3].lines, in skl_print_wm_changes()
2612 enast(old_wm->wm[4].ignore_lines), old_wm->wm[4].lines, in skl_print_wm_changes()
2613 enast(old_wm->wm[5].ignore_lines), old_wm->wm[5].lines, in skl_print_wm_changes()
2614 enast(old_wm->wm[6].ignore_lines), old_wm->wm[6].lines, in skl_print_wm_changes()
2615 enast(old_wm->wm[7].ignore_lines), old_wm->wm[7].lines, in skl_print_wm_changes()
2619 enast(new_wm->wm[0].ignore_lines), new_wm->wm[0].lines, in skl_print_wm_changes()
2620 enast(new_wm->wm[1].ignore_lines), new_wm->wm[1].lines, in skl_print_wm_changes()
2621 enast(new_wm->wm[2].ignore_lines), new_wm->wm[2].lines, in skl_print_wm_changes()
2622 enast(new_wm->wm[3].ignore_lines), new_wm->wm[3].lines, in skl_print_wm_changes()
2623 enast(new_wm->wm[4].ignore_lines), new_wm->wm[4].lines, in skl_print_wm_changes()
2624 enast(new_wm->wm[5].ignore_lines), new_wm->wm[5].lines, in skl_print_wm_changes()
2625 enast(new_wm->wm[6].ignore_lines), new_wm->wm[6].lines, in skl_print_wm_changes()
2626 enast(new_wm->wm[7].ignore_lines), new_wm->wm[7].lines, in skl_print_wm_changes()
2635 old_wm->wm[0].blocks, old_wm->wm[1].blocks, in skl_print_wm_changes()
2636 old_wm->wm[2].blocks, old_wm->wm[3].blocks, in skl_print_wm_changes()
2637 old_wm->wm[4].blocks, old_wm->wm[5].blocks, in skl_print_wm_changes()
2638 old_wm->wm[6].blocks, old_wm->wm[7].blocks, in skl_print_wm_changes()
2642 new_wm->wm[0].blocks, new_wm->wm[1].blocks, in skl_print_wm_changes()
2643 new_wm->wm[2].blocks, new_wm->wm[3].blocks, in skl_print_wm_changes()
2644 new_wm->wm[4].blocks, new_wm->wm[5].blocks, in skl_print_wm_changes()
2645 new_wm->wm[6].blocks, new_wm->wm[7].blocks, in skl_print_wm_changes()
2654 old_wm->wm[0].min_ddb_alloc, old_wm->wm[1].min_ddb_alloc, in skl_print_wm_changes()
2655 old_wm->wm[2].min_ddb_alloc, old_wm->wm[3].min_ddb_alloc, in skl_print_wm_changes()
2656 old_wm->wm[4].min_ddb_alloc, old_wm->wm[5].min_ddb_alloc, in skl_print_wm_changes()
2657 old_wm->wm[6].min_ddb_alloc, old_wm->wm[7].min_ddb_alloc, in skl_print_wm_changes()
2661 new_wm->wm[0].min_ddb_alloc, new_wm->wm[1].min_ddb_alloc, in skl_print_wm_changes()
2662 new_wm->wm[2].min_ddb_alloc, new_wm->wm[3].min_ddb_alloc, in skl_print_wm_changes()
2663 new_wm->wm[4].min_ddb_alloc, new_wm->wm[5].min_ddb_alloc, in skl_print_wm_changes()
2664 new_wm->wm[6].min_ddb_alloc, new_wm->wm[7].min_ddb_alloc, in skl_print_wm_changes()
2749 &old_crtc_state->wm.skl.optimal, in skl_wm_add_affected_planes()
2750 &new_crtc_state->wm.skl.optimal)) in skl_wm_add_affected_planes()
2820 struct skl_plane_wm *wm = &out->planes[plane_id]; in skl_pipe_wm_get_hw_state() local
2828 skl_wm_level_from_reg_val(val, &wm->wm[level]); in skl_pipe_wm_get_hw_state()
2836 skl_wm_level_from_reg_val(val, &wm->trans_wm); in skl_pipe_wm_get_hw_state()
2844 skl_wm_level_from_reg_val(val, &wm->sagv.wm0); in skl_pipe_wm_get_hw_state()
2851 skl_wm_level_from_reg_val(val, &wm->sagv.trans_wm); in skl_pipe_wm_get_hw_state()
2853 wm->sagv.wm0 = wm->wm[0]; in skl_pipe_wm_get_hw_state()
2854 wm->sagv.trans_wm = wm->trans_wm; in skl_pipe_wm_get_hw_state()
2876 memset(&crtc_state->wm.skl.optimal, 0, in skl_wm_get_hw_state()
2877 sizeof(crtc_state->wm.skl.optimal)); in skl_wm_get_hw_state()
2879 skl_pipe_wm_get_hw_state(crtc, &crtc_state->wm.skl.optimal); in skl_wm_get_hw_state()
2880 crtc_state->wm.skl.raw = crtc_state->wm.skl.optimal; in skl_wm_get_hw_state()
2886 &crtc_state->wm.skl.plane_ddb[plane_id]; in skl_wm_get_hw_state()
2888 &crtc_state->wm.skl.plane_ddb_y[plane_id]; in skl_wm_get_hw_state()
2909 crtc_state->wm.skl.ddb.start = mbus_offset + dbuf_state->ddb[pipe].start; in skl_wm_get_hw_state()
2910 crtc_state->wm.skl.ddb.end = mbus_offset + dbuf_state->ddb[pipe].end; in skl_wm_get_hw_state()
2914 skl_ddb_dbuf_slice_mask(i915, &crtc_state->wm.skl.ddb); in skl_wm_get_hw_state()
2938 entries[crtc->pipe] = crtc_state->wm.skl.ddb; in skl_dbuf_is_misconfigured()
2951 if (skl_ddb_allocation_overlaps(&crtc_state->wm.skl.ddb, entries, in skl_dbuf_is_misconfigured()
2991 memset(&crtc_state->wm.skl.ddb, 0, sizeof(crtc_state->wm.skl.ddb)); in skl_wm_sanitize()
3002 struct skl_pipe_wm wm; in intel_wm_state_verify() member
3004 const struct skl_pipe_wm *sw_wm = &new_crtc_state->wm.skl.optimal; in intel_wm_state_verify()
3016 skl_pipe_wm_get_hw_state(crtc, &hw->wm); in intel_wm_state_verify()
3035 hw_wm_level = &hw->wm.planes[plane->id].wm[level]; in intel_wm_state_verify()
3052 hw_wm_level = &hw->wm.planes[plane->id].trans_wm; in intel_wm_state_verify()
3067 hw_wm_level = &hw->wm.planes[plane->id].sagv.wm0; in intel_wm_state_verify()
3083 hw_wm_level = &hw->wm.planes[plane->id].sagv.trans_wm; in intel_wm_state_verify()
3101 sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb[PLANE_CURSOR]; in intel_wm_state_verify()
3117 return i915->display.wm.ipc_enabled; in skl_watermark_ipc_enabled()
3149 i915->display.wm.ipc_enabled = skl_watermark_ipc_can_enable(i915); in skl_watermark_ipc_init()
3156 u16 wm[], int max_level, int read_latency) in adjust_wm_latency() argument
3167 if (wm[level] == 0) { in adjust_wm_latency()
3169 wm[i] = 0; in adjust_wm_latency()
3183 if (wm[0] == 0) { in adjust_wm_latency()
3185 wm[level] += read_latency; in adjust_wm_latency()
3195 wm[0] += 1; in adjust_wm_latency()
3198 static void mtl_read_wm_latency(struct drm_i915_private *i915, u16 wm[]) in mtl_read_wm_latency() argument
3204 wm[0] = REG_FIELD_GET(MTL_LATENCY_LEVEL_EVEN_MASK, val); in mtl_read_wm_latency()
3205 wm[1] = REG_FIELD_GET(MTL_LATENCY_LEVEL_ODD_MASK, val); in mtl_read_wm_latency()
3208 wm[2] = REG_FIELD_GET(MTL_LATENCY_LEVEL_EVEN_MASK, val); in mtl_read_wm_latency()
3209 wm[3] = REG_FIELD_GET(MTL_LATENCY_LEVEL_ODD_MASK, val); in mtl_read_wm_latency()
3212 wm[4] = REG_FIELD_GET(MTL_LATENCY_LEVEL_EVEN_MASK, val); in mtl_read_wm_latency()
3213 wm[5] = REG_FIELD_GET(MTL_LATENCY_LEVEL_ODD_MASK, val); in mtl_read_wm_latency()
3215 adjust_wm_latency(i915, wm, max_level, 6); in mtl_read_wm_latency()
3218 static void skl_read_wm_latency(struct drm_i915_private *i915, u16 wm[]) in skl_read_wm_latency() argument
3234 wm[0] = REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_0_4_MASK, val) * mult; in skl_read_wm_latency()
3235 wm[1] = REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_1_5_MASK, val) * mult; in skl_read_wm_latency()
3236 wm[2] = REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_2_6_MASK, val) * mult; in skl_read_wm_latency()
3237 wm[3] = REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_3_7_MASK, val) * mult; in skl_read_wm_latency()
3247 wm[4] = REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_0_4_MASK, val) * mult; in skl_read_wm_latency()
3248 wm[5] = REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_1_5_MASK, val) * mult; in skl_read_wm_latency()
3249 wm[6] = REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_2_6_MASK, val) * mult; in skl_read_wm_latency()
3250 wm[7] = REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_3_7_MASK, val) * mult; in skl_read_wm_latency()
3252 adjust_wm_latency(i915, wm, max_level, read_latency); in skl_read_wm_latency()
3258 mtl_read_wm_latency(i915, i915->display.wm.skl_latency); in skl_setup_wm_latency()
3260 skl_read_wm_latency(i915, i915->display.wm.skl_latency); in skl_setup_wm_latency()
3262 intel_print_wm_latency(i915, "Gen9 Plane", i915->display.wm.skl_latency); in skl_setup_wm_latency()
3275 i915->display.funcs.wm = &skl_wm_funcs; in skl_wm_init()
3528 i915->display.wm.ipc_enabled = enable; in skl_watermark_ipc_status_write()