Lines Matching refs:dev_priv
89 struct drm_i915_private *dev_priv = to_i915(dev); in vlv_dsi_wait_for_fifo_empty() local
95 if (intel_de_wait_for_set(dev_priv, MIPI_GEN_FIFO_STAT(port), in vlv_dsi_wait_for_fifo_empty()
97 drm_err(&dev_priv->drm, "DPI FIFOs are not empty\n"); in vlv_dsi_wait_for_fifo_empty()
100 static void write_data(struct drm_i915_private *dev_priv, in write_data() argument
112 intel_de_write(dev_priv, reg, val); in write_data()
116 static void read_data(struct drm_i915_private *dev_priv, in read_data() argument
123 u32 val = intel_de_read(dev_priv, reg); in read_data()
135 struct drm_i915_private *dev_priv = to_i915(dev); in intel_dsi_host_transfer() local
164 if (intel_de_wait_for_clear(dev_priv, MIPI_GEN_FIFO_STAT(port), in intel_dsi_host_transfer()
166 drm_err(&dev_priv->drm, in intel_dsi_host_transfer()
169 write_data(dev_priv, data_reg, packet.payload, in intel_dsi_host_transfer()
174 intel_de_write(dev_priv, MIPI_INTR_STAT(port), in intel_dsi_host_transfer()
178 if (intel_de_wait_for_clear(dev_priv, MIPI_GEN_FIFO_STAT(port), in intel_dsi_host_transfer()
180 drm_err(&dev_priv->drm, in intel_dsi_host_transfer()
184 intel_de_write(dev_priv, ctrl_reg, in intel_dsi_host_transfer()
190 if (intel_de_wait_for_set(dev_priv, MIPI_INTR_STAT(port), in intel_dsi_host_transfer()
192 drm_err(&dev_priv->drm, in intel_dsi_host_transfer()
195 read_data(dev_priv, data_reg, msg->rx_buf, msg->rx_len); in intel_dsi_host_transfer()
230 struct drm_i915_private *dev_priv = to_i915(dev); in dpi_send_cmd() local
240 intel_de_write(dev_priv, MIPI_INTR_STAT(port), SPL_PKT_SENT_INTERRUPT); in dpi_send_cmd()
243 if (cmd == intel_de_read(dev_priv, MIPI_DPI_CONTROL(port))) in dpi_send_cmd()
244 drm_dbg_kms(&dev_priv->drm, in dpi_send_cmd()
247 intel_de_write(dev_priv, MIPI_DPI_CONTROL(port), cmd); in dpi_send_cmd()
250 if (intel_de_wait_for_set(dev_priv, MIPI_INTR_STAT(port), mask, 100)) in dpi_send_cmd()
251 drm_err(&dev_priv->drm, in dpi_send_cmd()
257 static void band_gap_reset(struct drm_i915_private *dev_priv) in band_gap_reset() argument
259 vlv_flisdsi_get(dev_priv); in band_gap_reset()
261 vlv_flisdsi_write(dev_priv, 0x08, 0x0001); in band_gap_reset()
262 vlv_flisdsi_write(dev_priv, 0x0F, 0x0005); in band_gap_reset()
263 vlv_flisdsi_write(dev_priv, 0x0F, 0x0025); in band_gap_reset()
265 vlv_flisdsi_write(dev_priv, 0x0F, 0x0000); in band_gap_reset()
266 vlv_flisdsi_write(dev_priv, 0x08, 0x0000); in band_gap_reset()
268 vlv_flisdsi_put(dev_priv); in band_gap_reset()
275 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_dsi_compute_config() local
282 drm_dbg_kms(&dev_priv->drm, "\n"); in intel_dsi_compute_config()
304 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { in intel_dsi_compute_config()
331 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in glk_dsi_enable_io() local
342 tmp = intel_de_read(dev_priv, MIPI_CTRL(port)); in glk_dsi_enable_io()
343 intel_de_write(dev_priv, MIPI_CTRL(port), in glk_dsi_enable_io()
348 tmp = intel_de_read(dev_priv, MIPI_CTRL(PORT_A)); in glk_dsi_enable_io()
350 intel_de_write(dev_priv, MIPI_CTRL(PORT_A), tmp); in glk_dsi_enable_io()
354 tmp = intel_de_read(dev_priv, MIPI_CTRL(port)); in glk_dsi_enable_io()
355 if (!(intel_de_read(dev_priv, MIPI_DEVICE_READY(port)) & DEVICE_READY)) in glk_dsi_enable_io()
359 intel_de_write(dev_priv, MIPI_CTRL(port), tmp); in glk_dsi_enable_io()
364 if (intel_de_wait_for_set(dev_priv, MIPI_CTRL(port), in glk_dsi_enable_io()
366 drm_err(&dev_priv->drm, "MIPIO port is powergated\n"); in glk_dsi_enable_io()
372 !(intel_de_read(dev_priv, MIPI_DEVICE_READY(port)) & DEVICE_READY); in glk_dsi_enable_io()
380 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in glk_dsi_device_ready() local
387 if (intel_de_wait_for_set(dev_priv, MIPI_CTRL(port), in glk_dsi_device_ready()
389 drm_err(&dev_priv->drm, "PHY is not ON\n"); in glk_dsi_device_ready()
393 val = intel_de_read(dev_priv, MIPI_CTRL(PORT_A)); in glk_dsi_device_ready()
394 intel_de_write(dev_priv, MIPI_CTRL(PORT_A), in glk_dsi_device_ready()
399 if (!(intel_de_read(dev_priv, MIPI_DEVICE_READY(port)) & DEVICE_READY)) { in glk_dsi_device_ready()
400 val = intel_de_read(dev_priv, MIPI_DEVICE_READY(port)); in glk_dsi_device_ready()
403 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val); in glk_dsi_device_ready()
407 val = intel_de_read(dev_priv, MIPI_DEVICE_READY(port)); in glk_dsi_device_ready()
410 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val); in glk_dsi_device_ready()
413 if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port), in glk_dsi_device_ready()
415 drm_err(&dev_priv->drm, "ULPS not active\n"); in glk_dsi_device_ready()
418 val = intel_de_read(dev_priv, MIPI_DEVICE_READY(port)); in glk_dsi_device_ready()
421 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val); in glk_dsi_device_ready()
424 val = intel_de_read(dev_priv, MIPI_DEVICE_READY(port)); in glk_dsi_device_ready()
427 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val); in glk_dsi_device_ready()
429 val = intel_de_read(dev_priv, MIPI_CTRL(port)); in glk_dsi_device_ready()
431 intel_de_write(dev_priv, MIPI_CTRL(port), val); in glk_dsi_device_ready()
437 if (intel_de_wait_for_set(dev_priv, MIPI_CTRL(port), in glk_dsi_device_ready()
439 drm_err(&dev_priv->drm, in glk_dsi_device_ready()
445 if (intel_de_wait_for_set(dev_priv, BXT_MIPI_PORT_CTRL(port), in glk_dsi_device_ready()
447 drm_err(&dev_priv->drm, in glk_dsi_device_ready()
454 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in bxt_dsi_device_ready() local
459 drm_dbg_kms(&dev_priv->drm, "\n"); in bxt_dsi_device_ready()
463 val = intel_de_read(dev_priv, BXT_MIPI_PORT_CTRL(port)); in bxt_dsi_device_ready()
464 intel_de_write(dev_priv, BXT_MIPI_PORT_CTRL(port), in bxt_dsi_device_ready()
471 val = intel_de_read(dev_priv, MIPI_DEVICE_READY(port)); in bxt_dsi_device_ready()
473 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val); in bxt_dsi_device_ready()
476 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val); in bxt_dsi_device_ready()
482 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in vlv_dsi_device_ready() local
487 drm_dbg_kms(&dev_priv->drm, "\n"); in vlv_dsi_device_ready()
489 vlv_flisdsi_get(dev_priv); in vlv_dsi_device_ready()
492 vlv_flisdsi_write(dev_priv, 0x04, 0x0004); in vlv_dsi_device_ready()
493 vlv_flisdsi_put(dev_priv); in vlv_dsi_device_ready()
496 band_gap_reset(dev_priv); in vlv_dsi_device_ready()
500 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), in vlv_dsi_device_ready()
508 val = intel_de_read(dev_priv, MIPI_PORT_CTRL(PORT_A)); in vlv_dsi_device_ready()
509 intel_de_write(dev_priv, MIPI_PORT_CTRL(PORT_A), in vlv_dsi_device_ready()
513 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), in vlv_dsi_device_ready()
517 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), in vlv_dsi_device_ready()
525 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_dsi_device_ready() local
527 if (IS_GEMINILAKE(dev_priv)) in intel_dsi_device_ready()
529 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) in intel_dsi_device_ready()
537 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in glk_dsi_enter_low_power_mode() local
544 val = intel_de_read(dev_priv, MIPI_DEVICE_READY(port)); in glk_dsi_enter_low_power_mode()
547 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val); in glk_dsi_enter_low_power_mode()
552 if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port), in glk_dsi_enter_low_power_mode()
554 drm_err(&dev_priv->drm, "PHY is not turning OFF\n"); in glk_dsi_enter_low_power_mode()
559 if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port), in glk_dsi_enter_low_power_mode()
561 drm_err(&dev_priv->drm, in glk_dsi_enter_low_power_mode()
568 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in glk_dsi_disable_mipi_io() local
574 tmp = intel_de_read(dev_priv, MIPI_CTRL(PORT_A)); in glk_dsi_disable_mipi_io()
576 intel_de_write(dev_priv, MIPI_CTRL(PORT_A), tmp); in glk_dsi_disable_mipi_io()
580 if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port), in glk_dsi_disable_mipi_io()
582 drm_err(&dev_priv->drm, "PHY is not turning OFF\n"); in glk_dsi_disable_mipi_io()
587 tmp = intel_de_read(dev_priv, MIPI_CTRL(port)); in glk_dsi_disable_mipi_io()
589 intel_de_write(dev_priv, MIPI_CTRL(port), tmp); in glk_dsi_disable_mipi_io()
601 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in vlv_dsi_clear_device_ready() local
605 drm_dbg_kms(&dev_priv->drm, "\n"); in vlv_dsi_clear_device_ready()
608 i915_reg_t port_ctrl = IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv) ? in vlv_dsi_clear_device_ready()
612 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), in vlv_dsi_clear_device_ready()
616 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), in vlv_dsi_clear_device_ready()
620 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), in vlv_dsi_clear_device_ready()
628 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv) || port == PORT_A) && in vlv_dsi_clear_device_ready()
629 intel_de_wait_for_clear(dev_priv, port_ctrl, in vlv_dsi_clear_device_ready()
631 drm_err(&dev_priv->drm, "DSI LP not going Low\n"); in vlv_dsi_clear_device_ready()
634 val = intel_de_read(dev_priv, port_ctrl); in vlv_dsi_clear_device_ready()
635 intel_de_write(dev_priv, port_ctrl, val & ~LP_OUTPUT_HOLD); in vlv_dsi_clear_device_ready()
638 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 0x00); in vlv_dsi_clear_device_ready()
646 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_dsi_port_enable() local
653 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { in intel_dsi_port_enable()
655 temp = intel_de_read(dev_priv, in intel_dsi_port_enable()
660 intel_de_write(dev_priv, MIPI_CTRL(port), in intel_dsi_port_enable()
664 temp = intel_de_read(dev_priv, VLV_CHICKEN_3); in intel_dsi_port_enable()
668 intel_de_write(dev_priv, VLV_CHICKEN_3, temp); in intel_dsi_port_enable()
673 i915_reg_t port_ctrl = IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv) ? in intel_dsi_port_enable()
677 temp = intel_de_read(dev_priv, port_ctrl); in intel_dsi_port_enable()
685 if (IS_BROXTON(dev_priv)) in intel_dsi_port_enable()
697 intel_de_write(dev_priv, port_ctrl, temp | DPI_ENABLE); in intel_dsi_port_enable()
698 intel_de_posting_read(dev_priv, port_ctrl); in intel_dsi_port_enable()
705 struct drm_i915_private *dev_priv = to_i915(dev); in intel_dsi_port_disable() local
710 i915_reg_t port_ctrl = IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv) ? in intel_dsi_port_disable()
715 temp = intel_de_read(dev_priv, port_ctrl); in intel_dsi_port_disable()
716 intel_de_write(dev_priv, port_ctrl, temp & ~DPI_ENABLE); in intel_dsi_port_disable()
717 intel_de_posting_read(dev_priv, port_ctrl); in intel_dsi_port_disable()
787 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_dsi_pre_enable() local
793 drm_dbg_kms(&dev_priv->drm, "\n"); in intel_dsi_pre_enable()
797 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); in intel_dsi_pre_enable()
803 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { in intel_dsi_pre_enable()
811 if (IS_BROXTON(dev_priv)) { in intel_dsi_pre_enable()
813 val = intel_de_read(dev_priv, BXT_P_CR_GT_DISP_PWRON); in intel_dsi_pre_enable()
814 intel_de_write(dev_priv, BXT_P_CR_GT_DISP_PWRON, in intel_dsi_pre_enable()
818 intel_de_write(dev_priv, BXT_P_DSI_REGULATOR_CFG, STAP_SELECT); in intel_dsi_pre_enable()
819 intel_de_write(dev_priv, BXT_P_DSI_REGULATOR_TX_CTRL, 0); in intel_dsi_pre_enable()
822 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { in intel_dsi_pre_enable()
826 val = intel_de_read(dev_priv, DSPCLK_GATE_D(dev_priv)); in intel_dsi_pre_enable()
828 intel_de_write(dev_priv, DSPCLK_GATE_D(dev_priv), val); in intel_dsi_pre_enable()
831 if (!IS_GEMINILAKE(dev_priv)) in intel_dsi_pre_enable()
850 if (IS_GEMINILAKE(dev_priv)) { in intel_dsi_pre_enable()
862 if (IS_GEMINILAKE(dev_priv) && !glk_cold_boot) in intel_dsi_pre_enable()
874 intel_de_write(dev_priv, in intel_dsi_pre_enable()
936 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_dsi_clear_device_ready() local
938 if (IS_GEMINILAKE(dev_priv)) in intel_dsi_clear_device_ready()
949 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_dsi_post_disable() local
954 drm_dbg_kms(&dev_priv->drm, "\n"); in intel_dsi_post_disable()
956 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { in intel_dsi_post_disable()
983 if (IS_BROXTON(dev_priv)) { in intel_dsi_post_disable()
985 intel_de_write(dev_priv, BXT_P_DSI_REGULATOR_CFG, STAP_SELECT); in intel_dsi_post_disable()
986 intel_de_write(dev_priv, BXT_P_DSI_REGULATOR_TX_CTRL, in intel_dsi_post_disable()
990 val = intel_de_read(dev_priv, BXT_P_CR_GT_DISP_PWRON); in intel_dsi_post_disable()
991 intel_de_write(dev_priv, BXT_P_CR_GT_DISP_PWRON, in intel_dsi_post_disable()
995 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { in intel_dsi_post_disable()
1002 val = intel_de_read(dev_priv, DSPCLK_GATE_D(dev_priv)); in intel_dsi_post_disable()
1004 intel_de_write(dev_priv, DSPCLK_GATE_D(dev_priv), val); in intel_dsi_post_disable()
1026 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_dsi_get_hw_state() local
1032 drm_dbg_kms(&dev_priv->drm, "\n"); in intel_dsi_get_hw_state()
1034 wakeref = intel_display_power_get_if_enabled(dev_priv, in intel_dsi_get_hw_state()
1044 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) && in intel_dsi_get_hw_state()
1045 !bxt_dsi_pll_is_enabled(dev_priv)) in intel_dsi_get_hw_state()
1050 i915_reg_t ctrl_reg = IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv) ? in intel_dsi_get_hw_state()
1052 bool enabled = intel_de_read(dev_priv, ctrl_reg) & DPI_ENABLE; in intel_dsi_get_hw_state()
1059 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && in intel_dsi_get_hw_state()
1061 enabled = intel_de_read(dev_priv, PIPECONF(PIPE_B)) & PIPECONF_ENABLE; in intel_dsi_get_hw_state()
1065 u32 tmp = intel_de_read(dev_priv, in intel_dsi_get_hw_state()
1073 if (!(intel_de_read(dev_priv, MIPI_DEVICE_READY(port)) & DEVICE_READY)) in intel_dsi_get_hw_state()
1076 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { in intel_dsi_get_hw_state()
1077 u32 tmp = intel_de_read(dev_priv, MIPI_CTRL(port)); in intel_dsi_get_hw_state()
1081 if (drm_WARN_ON(&dev_priv->drm, tmp > PIPE_C)) in intel_dsi_get_hw_state()
1094 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); in intel_dsi_get_hw_state()
1103 struct drm_i915_private *dev_priv = to_i915(dev); in bxt_dsi_get_pipe_config() local
1125 if (intel_de_read(dev_priv, BXT_MIPI_PORT_CTRL(port)) & DPI_ENABLE) in bxt_dsi_get_pipe_config()
1129 fmt = intel_de_read(dev_priv, MIPI_DSI_FUNC_PRG(port)) & VID_MODE_FORMAT_MASK; in bxt_dsi_get_pipe_config()
1141 intel_de_read(dev_priv, in bxt_dsi_get_pipe_config()
1144 intel_de_read(dev_priv, in bxt_dsi_get_pipe_config()
1147 intel_de_read(dev_priv, in bxt_dsi_get_pipe_config()
1151 hfp = intel_de_read(dev_priv, MIPI_HFP_COUNT(port)); in bxt_dsi_get_pipe_config()
1157 hsync = intel_de_read(dev_priv, MIPI_HSYNC_PADDING_COUNT(port)); in bxt_dsi_get_pipe_config()
1158 hbp = intel_de_read(dev_priv, MIPI_HBP_COUNT(port)); in bxt_dsi_get_pipe_config()
1175 vfp = intel_de_read(dev_priv, MIPI_VFP_COUNT(port)); in bxt_dsi_get_pipe_config()
1176 vsync = intel_de_read(dev_priv, MIPI_VSYNC_PADDING_COUNT(port)); in bxt_dsi_get_pipe_config()
1177 vbp = intel_de_read(dev_priv, MIPI_VBP_COUNT(port)); in bxt_dsi_get_pipe_config()
1266 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_dsi_get_config() local
1270 drm_dbg_kms(&dev_priv->drm, "\n"); in intel_dsi_get_config()
1274 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { in intel_dsi_get_config()
1307 struct drm_i915_private *dev_priv = to_i915(dev); in set_dsi_timings() local
1342 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { in set_dsi_timings()
1349 intel_de_write(dev_priv, BXT_MIPI_TRANS_HACTIVE(port), in set_dsi_timings()
1351 intel_de_write(dev_priv, BXT_MIPI_TRANS_VACTIVE(port), in set_dsi_timings()
1353 intel_de_write(dev_priv, BXT_MIPI_TRANS_VTOTAL(port), in set_dsi_timings()
1357 intel_de_write(dev_priv, MIPI_HACTIVE_AREA_COUNT(port), in set_dsi_timings()
1359 intel_de_write(dev_priv, MIPI_HFP_COUNT(port), hfp); in set_dsi_timings()
1363 intel_de_write(dev_priv, MIPI_HSYNC_PADDING_COUNT(port), in set_dsi_timings()
1365 intel_de_write(dev_priv, MIPI_HBP_COUNT(port), hbp); in set_dsi_timings()
1368 intel_de_write(dev_priv, MIPI_VFP_COUNT(port), vfp); in set_dsi_timings()
1369 intel_de_write(dev_priv, MIPI_VSYNC_PADDING_COUNT(port), in set_dsi_timings()
1371 intel_de_write(dev_priv, MIPI_VBP_COUNT(port), vbp); in set_dsi_timings()
1397 struct drm_i915_private *dev_priv = to_i915(dev); in intel_dsi_prepare() local
1406 drm_dbg_kms(&dev_priv->drm, "pipe %c\n", pipe_name(crtc->pipe)); in intel_dsi_prepare()
1417 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { in intel_dsi_prepare()
1422 tmp = intel_de_read(dev_priv, MIPI_CTRL(PORT_A)); in intel_dsi_prepare()
1424 intel_de_write(dev_priv, MIPI_CTRL(PORT_A), in intel_dsi_prepare()
1428 tmp = intel_de_read(dev_priv, MIPI_CTRL(port)); in intel_dsi_prepare()
1430 intel_de_write(dev_priv, MIPI_CTRL(port), in intel_dsi_prepare()
1432 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { in intel_dsi_prepare()
1435 tmp = intel_de_read(dev_priv, MIPI_CTRL(port)); in intel_dsi_prepare()
1439 intel_de_write(dev_priv, MIPI_CTRL(port), tmp); in intel_dsi_prepare()
1443 intel_de_write(dev_priv, MIPI_INTR_STAT(port), 0xffffffff); in intel_dsi_prepare()
1444 intel_de_write(dev_priv, MIPI_INTR_EN(port), 0xffffffff); in intel_dsi_prepare()
1446 intel_de_write(dev_priv, MIPI_DPHY_PARAM(port), in intel_dsi_prepare()
1449 intel_de_write(dev_priv, MIPI_DPI_RESOLUTION(port), in intel_dsi_prepare()
1470 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { in intel_dsi_prepare()
1477 intel_de_write(dev_priv, MIPI_DSI_FUNC_PRG(port), val); in intel_dsi_prepare()
1498 intel_de_write(dev_priv, MIPI_HS_TX_TIMEOUT(port), in intel_dsi_prepare()
1501 intel_de_write(dev_priv, MIPI_HS_TX_TIMEOUT(port), in intel_dsi_prepare()
1504 intel_de_write(dev_priv, MIPI_LP_RX_TIMEOUT(port), in intel_dsi_prepare()
1506 intel_de_write(dev_priv, MIPI_TURN_AROUND_TIMEOUT(port), in intel_dsi_prepare()
1508 intel_de_write(dev_priv, MIPI_DEVICE_RESET_TIMER(port), in intel_dsi_prepare()
1514 intel_de_write(dev_priv, MIPI_INIT_COUNT(port), in intel_dsi_prepare()
1517 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) && in intel_dsi_prepare()
1525 intel_de_write(dev_priv, in intel_dsi_prepare()
1531 intel_de_write(dev_priv, MIPI_EOT_DISABLE(port), tmp); in intel_dsi_prepare()
1534 intel_de_write(dev_priv, MIPI_INIT_COUNT(port), in intel_dsi_prepare()
1542 intel_de_write(dev_priv, MIPI_HIGH_LOW_SWITCH_COUNT(port), in intel_dsi_prepare()
1551 intel_de_write(dev_priv, MIPI_LP_BYTECLK(port), in intel_dsi_prepare()
1554 if (IS_GEMINILAKE(dev_priv)) { in intel_dsi_prepare()
1555 intel_de_write(dev_priv, MIPI_TLPX_TIME_COUNT(port), in intel_dsi_prepare()
1558 intel_de_write(dev_priv, MIPI_CLK_LANE_TIMING(port), in intel_dsi_prepare()
1567 intel_de_write(dev_priv, MIPI_DBI_BW_CTRL(port), in intel_dsi_prepare()
1570 intel_de_write(dev_priv, MIPI_CLK_LANE_SWITCH_TIME_CNT(port), in intel_dsi_prepare()
1598 intel_de_write(dev_priv, MIPI_VIDEO_MODE_FORMAT(port), fmt); in intel_dsi_prepare()
1605 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_dsi_unprepare() local
1610 if (IS_GEMINILAKE(dev_priv)) in intel_dsi_unprepare()
1615 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 0x0); in intel_dsi_unprepare()
1617 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) in intel_dsi_unprepare()
1621 intel_de_write(dev_priv, MIPI_EOT_DISABLE(port), CLOCKSTOP); in intel_dsi_unprepare()
1623 val = intel_de_read(dev_priv, MIPI_DSI_FUNC_PRG(port)); in intel_dsi_unprepare()
1625 intel_de_write(dev_priv, MIPI_DSI_FUNC_PRG(port), val); in intel_dsi_unprepare()
1627 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 0x1); in intel_dsi_unprepare()
1684 struct drm_i915_private *dev_priv = to_i915(dev); in vlv_dphy_param_init() local
1733 mul = IS_GEMINILAKE(dev_priv) ? 8 : 2; in vlv_dphy_param_init()
1741 drm_dbg_kms(&dev_priv->drm, "prepare count too high %u\n", in vlv_dphy_param_init()
1762 drm_dbg_kms(&dev_priv->drm, "exit zero count too high %u\n", in vlv_dphy_param_init()
1773 drm_dbg_kms(&dev_priv->drm, "clock zero count too high %u\n", in vlv_dphy_param_init()
1783 drm_dbg_kms(&dev_priv->drm, "trail count too high %u\n", in vlv_dphy_param_init()
1847 void vlv_dsi_init(struct drm_i915_private *dev_priv) in vlv_dsi_init() argument
1858 drm_dbg_kms(&dev_priv->drm, "\n"); in vlv_dsi_init()
1861 if (!intel_bios_is_dsi_present(dev_priv, &port)) in vlv_dsi_init()
1864 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) in vlv_dsi_init()
1865 dev_priv->display.dsi.mmio_base = BXT_MIPI_BASE; in vlv_dsi_init()
1867 dev_priv->display.dsi.mmio_base = VLV_MIPI_BASE; in vlv_dsi_init()
1885 drm_encoder_init(&dev_priv->drm, encoder, &intel_dsi_funcs, DRM_MODE_ENCODER_DSI, in vlv_dsi_init()
1890 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) in vlv_dsi_init()
1910 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) in vlv_dsi_init()
1919 intel_bios_init_panel_late(dev_priv, &intel_connector->panel, NULL, NULL); in vlv_dsi_init()
1926 if (drm_WARN_ON(&dev_priv->drm, intel_connector->panel.vbt.dsi.bl_ports & ~intel_dsi->ports)) in vlv_dsi_init()
1929 if (drm_WARN_ON(&dev_priv->drm, intel_connector->panel.vbt.dsi.cabc_ports & ~intel_dsi->ports)) in vlv_dsi_init()
1945 drm_dbg_kms(&dev_priv->drm, "no device found\n"); in vlv_dsi_init()
1952 drm_dbg_kms(&dev_priv->drm, "Calculated pclk %d GOP %d\n", in vlv_dsi_init()
1956 drm_dbg_kms(&dev_priv->drm, "Using GOP pclk\n"); in vlv_dsi_init()
1968 drm_connector_init(&dev_priv->drm, connector, &intel_dsi_connector_funcs, in vlv_dsi_init()
1977 mutex_lock(&dev_priv->drm.mode_config.mutex); in vlv_dsi_init()
1979 mutex_unlock(&dev_priv->drm.mode_config.mutex); in vlv_dsi_init()
1982 drm_dbg_kms(&dev_priv->drm, "no fixed mode\n"); in vlv_dsi_init()