Lines Matching refs:wal
95 static void wa_init_start(struct i915_wa_list *wal, struct intel_gt *gt, in wa_init_start() argument
98 wal->gt = gt; in wa_init_start()
99 wal->name = name; in wa_init_start()
100 wal->engine_name = engine_name; in wa_init_start()
105 static void wa_init_finish(struct i915_wa_list *wal) in wa_init_finish() argument
108 if (!IS_ALIGNED(wal->count, WA_LIST_CHUNK)) { in wa_init_finish()
109 struct i915_wa *list = kmemdup(wal->list, in wa_init_finish()
110 wal->count * sizeof(*list), in wa_init_finish()
114 kfree(wal->list); in wa_init_finish()
115 wal->list = list; in wa_init_finish()
119 if (!wal->count) in wa_init_finish()
122 drm_dbg(&wal->gt->i915->drm, "Initialized %u %s workarounds on %s\n", in wa_init_finish()
123 wal->wa_count, wal->name, wal->engine_name); in wa_init_finish()
126 static void _wa_add(struct i915_wa_list *wal, const struct i915_wa *wa) in _wa_add() argument
129 struct drm_i915_private *i915 = wal->gt->i915; in _wa_add()
130 unsigned int start = 0, end = wal->count; in _wa_add()
136 if (IS_ALIGNED(wal->count, grow)) { /* Either uninitialized or full. */ in _wa_add()
139 list = kmalloc_array(ALIGN(wal->count + 1, grow), sizeof(*wa), in _wa_add()
146 if (wal->list) { in _wa_add()
147 memcpy(list, wal->list, sizeof(*wa) * wal->count); in _wa_add()
148 kfree(wal->list); in _wa_add()
151 wal->list = list; in _wa_add()
157 if (i915_mmio_reg_offset(wal->list[mid].reg) < addr) { in _wa_add()
159 } else if (i915_mmio_reg_offset(wal->list[mid].reg) > addr) { in _wa_add()
162 wa_ = &wal->list[mid]; in _wa_add()
173 wal->wa_count++; in _wa_add()
181 wal->wa_count++; in _wa_add()
182 wa_ = &wal->list[wal->count++]; in _wa_add()
185 while (wa_-- > wal->list) { in _wa_add()
196 static void wa_add(struct i915_wa_list *wal, i915_reg_t reg, in wa_add() argument
207 _wa_add(wal, &wa); in wa_add()
210 static void wa_mcr_add(struct i915_wa_list *wal, i915_mcr_reg_t reg, in wa_mcr_add() argument
222 _wa_add(wal, &wa); in wa_mcr_add()
226 wa_write_clr_set(struct i915_wa_list *wal, i915_reg_t reg, u32 clear, u32 set) in wa_write_clr_set() argument
228 wa_add(wal, reg, clear, set, clear, false); in wa_write_clr_set()
232 wa_mcr_write_clr_set(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 clear, u32 set) in wa_mcr_write_clr_set() argument
234 wa_mcr_add(wal, reg, clear, set, clear, false); in wa_mcr_write_clr_set()
238 wa_write(struct i915_wa_list *wal, i915_reg_t reg, u32 set) in wa_write() argument
240 wa_write_clr_set(wal, reg, ~0, set); in wa_write()
244 wa_mcr_write(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 set) in wa_mcr_write() argument
246 wa_mcr_write_clr_set(wal, reg, ~0, set); in wa_mcr_write()
250 wa_write_or(struct i915_wa_list *wal, i915_reg_t reg, u32 set) in wa_write_or() argument
252 wa_write_clr_set(wal, reg, set, set); in wa_write_or()
256 wa_mcr_write_or(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 set) in wa_mcr_write_or() argument
258 wa_mcr_write_clr_set(wal, reg, set, set); in wa_mcr_write_or()
262 wa_write_clr(struct i915_wa_list *wal, i915_reg_t reg, u32 clr) in wa_write_clr() argument
264 wa_write_clr_set(wal, reg, clr, 0); in wa_write_clr()
268 wa_mcr_write_clr(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 clr) in wa_mcr_write_clr() argument
270 wa_mcr_write_clr_set(wal, reg, clr, 0); in wa_mcr_write_clr()
285 wa_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val) in wa_masked_en() argument
287 wa_add(wal, reg, 0, _MASKED_BIT_ENABLE(val), val, true); in wa_masked_en()
291 wa_mcr_masked_en(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 val) in wa_mcr_masked_en() argument
293 wa_mcr_add(wal, reg, 0, _MASKED_BIT_ENABLE(val), val, true); in wa_mcr_masked_en()
297 wa_masked_dis(struct i915_wa_list *wal, i915_reg_t reg, u32 val) in wa_masked_dis() argument
299 wa_add(wal, reg, 0, _MASKED_BIT_DISABLE(val), val, true); in wa_masked_dis()
303 wa_mcr_masked_dis(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 val) in wa_mcr_masked_dis() argument
305 wa_mcr_add(wal, reg, 0, _MASKED_BIT_DISABLE(val), val, true); in wa_mcr_masked_dis()
309 wa_masked_field_set(struct i915_wa_list *wal, i915_reg_t reg, in wa_masked_field_set() argument
312 wa_add(wal, reg, 0, _MASKED_FIELD(mask, val), mask, true); in wa_masked_field_set()
316 wa_mcr_masked_field_set(struct i915_wa_list *wal, i915_mcr_reg_t reg, in wa_mcr_masked_field_set() argument
319 wa_mcr_add(wal, reg, 0, _MASKED_FIELD(mask, val), mask, true); in wa_mcr_masked_field_set()
323 struct i915_wa_list *wal) in gen6_ctx_workarounds_init() argument
325 wa_masked_en(wal, INSTPM, INSTPM_FORCE_ORDERING); in gen6_ctx_workarounds_init()
329 struct i915_wa_list *wal) in gen7_ctx_workarounds_init() argument
331 wa_masked_en(wal, INSTPM, INSTPM_FORCE_ORDERING); in gen7_ctx_workarounds_init()
335 struct i915_wa_list *wal) in gen8_ctx_workarounds_init() argument
337 wa_masked_en(wal, INSTPM, INSTPM_FORCE_ORDERING); in gen8_ctx_workarounds_init()
340 wa_masked_en(wal, RING_MI_MODE(RENDER_RING_BASE), ASYNC_FLIP_PERF_DISABLE); in gen8_ctx_workarounds_init()
343 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN, in gen8_ctx_workarounds_init()
352 wa_masked_en(wal, HDC_CHICKEN0, in gen8_ctx_workarounds_init()
364 wa_masked_dis(wal, CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE); in gen8_ctx_workarounds_init()
367 wa_masked_en(wal, CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE); in gen8_ctx_workarounds_init()
377 wa_masked_field_set(wal, GEN7_GT_MODE, in gen8_ctx_workarounds_init()
383 struct i915_wa_list *wal) in bdw_ctx_workarounds_init() argument
387 gen8_ctx_workarounds_init(engine, wal); in bdw_ctx_workarounds_init()
390 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE); in bdw_ctx_workarounds_init()
397 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2, in bdw_ctx_workarounds_init()
400 wa_mcr_masked_en(wal, GEN8_HALF_SLICE_CHICKEN3, in bdw_ctx_workarounds_init()
403 wa_masked_en(wal, HDC_CHICKEN0, in bdw_ctx_workarounds_init()
411 struct i915_wa_list *wal) in chv_ctx_workarounds_init() argument
413 gen8_ctx_workarounds_init(engine, wal); in chv_ctx_workarounds_init()
416 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE); in chv_ctx_workarounds_init()
419 wa_masked_en(wal, HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X); in chv_ctx_workarounds_init()
423 struct i915_wa_list *wal) in gen9_ctx_workarounds_init() argument
433 wa_masked_en(wal, COMMON_SLICE_CHICKEN2, in gen9_ctx_workarounds_init()
435 wa_mcr_masked_en(wal, GEN9_HALF_SLICE_CHICKEN7, in gen9_ctx_workarounds_init()
441 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN, in gen9_ctx_workarounds_init()
447 wa_mcr_masked_en(wal, GEN9_HALF_SLICE_CHICKEN7, in gen9_ctx_workarounds_init()
453 wa_masked_en(wal, CACHE_MODE_1, in gen9_ctx_workarounds_init()
458 wa_mcr_masked_dis(wal, GEN9_HALF_SLICE_CHICKEN5, in gen9_ctx_workarounds_init()
462 wa_masked_en(wal, HDC_CHICKEN0, in gen9_ctx_workarounds_init()
480 wa_masked_en(wal, HDC_CHICKEN0, in gen9_ctx_workarounds_init()
488 wa_mcr_masked_en(wal, GEN8_HALF_SLICE_CHICKEN3, in gen9_ctx_workarounds_init()
492 wa_mcr_masked_en(wal, HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE); in gen9_ctx_workarounds_init()
506 wa_masked_dis(wal, GEN8_CS_CHICKEN1, GEN9_PREEMPT_3D_OBJECT_LEVEL); in gen9_ctx_workarounds_init()
509 wa_masked_field_set(wal, GEN8_CS_CHICKEN1, in gen9_ctx_workarounds_init()
515 wa_masked_en(wal, GEN9_WM_CHICKEN3, GEN9_FACTOR_IN_CLR_VAL_HIZ); in gen9_ctx_workarounds_init()
519 struct i915_wa_list *wal) in skl_tune_iz_hashing() argument
549 wa_masked_field_set(wal, GEN7_GT_MODE, in skl_tune_iz_hashing()
559 struct i915_wa_list *wal) in skl_ctx_workarounds_init() argument
561 gen9_ctx_workarounds_init(engine, wal); in skl_ctx_workarounds_init()
562 skl_tune_iz_hashing(engine, wal); in skl_ctx_workarounds_init()
566 struct i915_wa_list *wal) in bxt_ctx_workarounds_init() argument
568 gen9_ctx_workarounds_init(engine, wal); in bxt_ctx_workarounds_init()
571 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN, in bxt_ctx_workarounds_init()
575 wa_masked_en(wal, COMMON_SLICE_CHICKEN2, in bxt_ctx_workarounds_init()
580 struct i915_wa_list *wal) in kbl_ctx_workarounds_init() argument
584 gen9_ctx_workarounds_init(engine, wal); in kbl_ctx_workarounds_init()
588 wa_masked_en(wal, COMMON_SLICE_CHICKEN2, in kbl_ctx_workarounds_init()
592 wa_mcr_masked_en(wal, GEN8_HALF_SLICE_CHICKEN1, in kbl_ctx_workarounds_init()
597 struct i915_wa_list *wal) in glk_ctx_workarounds_init() argument
599 gen9_ctx_workarounds_init(engine, wal); in glk_ctx_workarounds_init()
602 wa_masked_en(wal, COMMON_SLICE_CHICKEN2, in glk_ctx_workarounds_init()
607 struct i915_wa_list *wal) in cfl_ctx_workarounds_init() argument
609 gen9_ctx_workarounds_init(engine, wal); in cfl_ctx_workarounds_init()
612 wa_masked_en(wal, COMMON_SLICE_CHICKEN2, in cfl_ctx_workarounds_init()
616 wa_mcr_masked_en(wal, GEN8_HALF_SLICE_CHICKEN1, in cfl_ctx_workarounds_init()
621 struct i915_wa_list *wal) in icl_ctx_workarounds_init() argument
624 wa_write(wal, in icl_ctx_workarounds_init()
636 wa_mcr_masked_en(wal, ICL_HDC_MODE, HDC_FORCE_NON_COHERENT); in icl_ctx_workarounds_init()
639 wa_mcr_add(wal, GEN10_CACHE_MODE_SS, 0, in icl_ctx_workarounds_init()
645 wa_masked_field_set(wal, GEN8_CS_CHICKEN1, in icl_ctx_workarounds_init()
650 wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE, in icl_ctx_workarounds_init()
654 wa_write(wal, IVB_FBC_RT_BASE, 0xFFFFFFFF & ~ILK_FBC_RT_VALID); in icl_ctx_workarounds_init()
655 wa_write_clr_set(wal, IVB_FBC_RT_BASE_UPPER, in icl_ctx_workarounds_init()
660 wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN4, GEN11_DIS_PICK_2ND_EU); in icl_ctx_workarounds_init()
668 struct i915_wa_list *wal) in dg2_ctx_gt_tuning_init() argument
670 wa_mcr_masked_en(wal, CHICKEN_RASTER_2, TBIMR_FAST_CLIP); in dg2_ctx_gt_tuning_init()
671 wa_mcr_write_clr_set(wal, XEHP_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK, in dg2_ctx_gt_tuning_init()
673 wa_mcr_add(wal, in dg2_ctx_gt_tuning_init()
685 struct i915_wa_list *wal) in gen12_ctx_gt_tuning_init() argument
700 wa_add(wal, in gen12_ctx_gt_tuning_init()
708 struct i915_wa_list *wal) in gen12_ctx_workarounds_init() argument
712 gen12_ctx_gt_tuning_init(engine, wal); in gen12_ctx_workarounds_init()
726 wa_masked_en(wal, GEN11_COMMON_SLICE_CHICKEN3, in gen12_ctx_workarounds_init()
730 wa_masked_field_set(wal, GEN8_CS_CHICKEN1, in gen12_ctx_workarounds_init()
740 wa_add(wal, in gen12_ctx_workarounds_init()
748 wa_masked_en(wal, HIZ_CHICKEN, HZ_DEPTH_TEST_LE_GE_OPT_DISABLE); in gen12_ctx_workarounds_init()
752 struct i915_wa_list *wal) in dg1_ctx_workarounds_init() argument
754 gen12_ctx_workarounds_init(engine, wal); in dg1_ctx_workarounds_init()
757 wa_masked_dis(wal, GEN11_COMMON_SLICE_CHICKEN3, in dg1_ctx_workarounds_init()
761 wa_masked_en(wal, HIZ_CHICKEN, in dg1_ctx_workarounds_init()
766 struct i915_wa_list *wal) in dg2_ctx_workarounds_init() argument
768 dg2_ctx_gt_tuning_init(engine, wal); in dg2_ctx_workarounds_init()
772 wa_mcr_masked_dis(wal, VFLSKPD, DIS_MULT_MISS_RD_SQUASH); in dg2_ctx_workarounds_init()
773 wa_mcr_masked_en(wal, VFLSKPD, DIS_OVER_FETCH_CACHE); in dg2_ctx_workarounds_init()
778 wa_mcr_masked_en(wal, XEHP_COMMON_SLICE_CHICKEN3, in dg2_ctx_workarounds_init()
786 wa_mcr_masked_en(wal, XEHP_COMMON_SLICE_CHICKEN3, in dg2_ctx_workarounds_init()
791 wa_mcr_masked_en(wal, XEHP_SLICE_COMMON_ECO_CHICKEN1, in dg2_ctx_workarounds_init()
797 wa_masked_field_set(wal, VF_PREEMPTION, PREEMPTION_VERTEX_COUNT, 0x4000); in dg2_ctx_workarounds_init()
802 wa_mcr_masked_en(wal, XEHP_PSS_MODE2, SCOREBOARD_STALL_FLUSH_CONTROL); in dg2_ctx_workarounds_init()
805 wa_mcr_masked_en(wal, CHICKEN_RASTER_1, DIS_SF_ROUND_NEAREST_EVEN); in dg2_ctx_workarounds_init()
808 wa_masked_en(wal, CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE); in dg2_ctx_workarounds_init()
812 struct i915_wa_list *wal) in mtl_ctx_workarounds_init() argument
819 wa_masked_field_set(wal, VF_PREEMPTION, in mtl_ctx_workarounds_init()
823 wa_mcr_masked_en(wal, XEHP_SLICE_COMMON_ECO_CHICKEN1, in mtl_ctx_workarounds_init()
827 wa_mcr_masked_en(wal, VFLSKPD, VF_PREFETCH_TLB_DIS); in mtl_ctx_workarounds_init()
830 wa_mcr_masked_en(wal, XEHP_PSS_MODE2, SCOREBOARD_STALL_FLUSH_CONTROL); in mtl_ctx_workarounds_init()
834 wa_masked_en(wal, CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE); in mtl_ctx_workarounds_init()
838 struct i915_wa_list *wal) in fakewa_disable_nestedbb_mode() argument
865 wa_masked_dis(wal, RING_MI_MODE(engine->mmio_base), TGL_NESTED_BB_EN); in fakewa_disable_nestedbb_mode()
869 struct i915_wa_list *wal) in gen12_ctx_gt_mocs_init() argument
880 wa_write_clr_set(wal, in gen12_ctx_gt_mocs_init()
895 struct i915_wa_list *wal) in gen12_ctx_gt_fake_wa_init() argument
898 fakewa_disable_nestedbb_mode(engine, wal); in gen12_ctx_gt_fake_wa_init()
900 gen12_ctx_gt_mocs_init(engine, wal); in gen12_ctx_gt_fake_wa_init()
905 struct i915_wa_list *wal, in __intel_engine_init_ctx_wa() argument
910 wa_init_start(wal, engine->gt, name, engine->name); in __intel_engine_init_ctx_wa()
918 gen12_ctx_gt_fake_wa_init(engine, wal); in __intel_engine_init_ctx_wa()
924 mtl_ctx_workarounds_init(engine, wal); in __intel_engine_init_ctx_wa()
928 dg2_ctx_workarounds_init(engine, wal); in __intel_engine_init_ctx_wa()
932 dg1_ctx_workarounds_init(engine, wal); in __intel_engine_init_ctx_wa()
934 gen12_ctx_workarounds_init(engine, wal); in __intel_engine_init_ctx_wa()
936 icl_ctx_workarounds_init(engine, wal); in __intel_engine_init_ctx_wa()
938 cfl_ctx_workarounds_init(engine, wal); in __intel_engine_init_ctx_wa()
940 glk_ctx_workarounds_init(engine, wal); in __intel_engine_init_ctx_wa()
942 kbl_ctx_workarounds_init(engine, wal); in __intel_engine_init_ctx_wa()
944 bxt_ctx_workarounds_init(engine, wal); in __intel_engine_init_ctx_wa()
946 skl_ctx_workarounds_init(engine, wal); in __intel_engine_init_ctx_wa()
948 chv_ctx_workarounds_init(engine, wal); in __intel_engine_init_ctx_wa()
950 bdw_ctx_workarounds_init(engine, wal); in __intel_engine_init_ctx_wa()
952 gen7_ctx_workarounds_init(engine, wal); in __intel_engine_init_ctx_wa()
954 gen6_ctx_workarounds_init(engine, wal); in __intel_engine_init_ctx_wa()
961 wa_init_finish(wal); in __intel_engine_init_ctx_wa()
971 struct i915_wa_list *wal = &rq->engine->ctx_wa_list; in intel_engine_emit_ctx_wa() local
977 if (wal->count == 0) in intel_engine_emit_ctx_wa()
984 cs = intel_ring_begin(rq, (wal->count * 2 + 2)); in intel_engine_emit_ctx_wa()
988 *cs++ = MI_LOAD_REGISTER_IMM(wal->count); in intel_engine_emit_ctx_wa()
989 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { in intel_engine_emit_ctx_wa()
1006 struct i915_wa_list *wal) in gen4_gt_workarounds_init() argument
1009 wa_masked_dis(wal, CACHE_MODE_0, RC_OP_FLUSH_ENABLE); in gen4_gt_workarounds_init()
1013 g4x_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) in g4x_gt_workarounds_init() argument
1015 gen4_gt_workarounds_init(gt, wal); in g4x_gt_workarounds_init()
1018 wa_masked_en(wal, CACHE_MODE_0, CM0_PIPELINED_RENDER_FLUSH_DISABLE); in g4x_gt_workarounds_init()
1022 ilk_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) in ilk_gt_workarounds_init() argument
1024 g4x_gt_workarounds_init(gt, wal); in ilk_gt_workarounds_init()
1026 wa_masked_en(wal, _3D_CHICKEN2, _3D_CHICKEN2_WM_READ_PIPELINED); in ilk_gt_workarounds_init()
1030 snb_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) in snb_gt_workarounds_init() argument
1035 ivb_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) in ivb_gt_workarounds_init() argument
1038 wa_masked_dis(wal, in ivb_gt_workarounds_init()
1043 wa_write(wal, GEN7_L3CNTLREG1, GEN7_WA_FOR_GEN7_L3_CONTROL); in ivb_gt_workarounds_init()
1044 wa_write(wal, GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE); in ivb_gt_workarounds_init()
1047 wa_write_clr(wal, GEN7_L3SQCREG4, L3SQ_URB_READ_CAM_MATCH_DISABLE); in ivb_gt_workarounds_init()
1051 vlv_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) in vlv_gt_workarounds_init() argument
1054 wa_write_clr(wal, GEN7_L3SQCREG4, L3SQ_URB_READ_CAM_MATCH_DISABLE); in vlv_gt_workarounds_init()
1060 wa_write(wal, GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE); in vlv_gt_workarounds_init()
1064 hsw_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) in hsw_gt_workarounds_init() argument
1067 wa_write(wal, HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE); in hsw_gt_workarounds_init()
1069 wa_add(wal, in hsw_gt_workarounds_init()
1075 wa_write_clr(wal, GEN7_FF_THREAD_MODE, GEN7_FF_VS_REF_CNT_FFME); in hsw_gt_workarounds_init()
1079 gen9_wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal) in gen9_wa_init_mcr() argument
1113 wa_write_clr_set(wal, GEN8_MCR_SELECTOR, mcr_mask, mcr); in gen9_wa_init_mcr()
1117 gen9_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) in gen9_gt_workarounds_init() argument
1122 gen9_wa_init_mcr(i915, wal); in gen9_gt_workarounds_init()
1126 wa_write_or(wal, in gen9_gt_workarounds_init()
1136 wa_write_or(wal, in gen9_gt_workarounds_init()
1142 wa_write_or(wal, in gen9_gt_workarounds_init()
1148 skl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) in skl_gt_workarounds_init() argument
1150 gen9_gt_workarounds_init(gt, wal); in skl_gt_workarounds_init()
1153 wa_write_or(wal, in skl_gt_workarounds_init()
1159 wa_write_or(wal, in skl_gt_workarounds_init()
1165 kbl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) in kbl_gt_workarounds_init() argument
1167 gen9_gt_workarounds_init(gt, wal); in kbl_gt_workarounds_init()
1171 wa_write_or(wal, in kbl_gt_workarounds_init()
1176 wa_write_or(wal, in kbl_gt_workarounds_init()
1181 wa_write_or(wal, in kbl_gt_workarounds_init()
1187 glk_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) in glk_gt_workarounds_init() argument
1189 gen9_gt_workarounds_init(gt, wal); in glk_gt_workarounds_init()
1193 cfl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) in cfl_gt_workarounds_init() argument
1195 gen9_gt_workarounds_init(gt, wal); in cfl_gt_workarounds_init()
1198 wa_write_or(wal, in cfl_gt_workarounds_init()
1203 wa_write_or(wal, in cfl_gt_workarounds_init()
1208 static void __set_mcr_steering(struct i915_wa_list *wal, in __set_mcr_steering() argument
1217 wa_write_clr_set(wal, steering_reg, mcr_mask, mcr); in __set_mcr_steering()
1228 static void __add_mcr_wa(struct intel_gt *gt, struct i915_wa_list *wal, in __add_mcr_wa() argument
1231 __set_mcr_steering(wal, GEN8_MCR_SELECTOR, slice, subslice); in __add_mcr_wa()
1240 icl_wa_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal) in icl_wa_init_mcr() argument
1267 __add_mcr_wa(gt, wal, 0, subslice); in icl_wa_init_mcr()
1271 xehp_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal) in xehp_init_mcr() argument
1337 __add_mcr_wa(gt, wal, slice, subslice); in xehp_init_mcr()
1348 __set_mcr_steering(wal, MCFG_MCR_SELECTOR, 0, 2); in xehp_init_mcr()
1349 __set_mcr_steering(wal, SF_MCR_SELECTOR, 0, 2); in xehp_init_mcr()
1356 __set_mcr_steering(wal, GAM_MCR_SELECTOR, 1, 0); in xehp_init_mcr()
1360 pvc_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal) in pvc_init_mcr() argument
1370 __add_mcr_wa(gt, wal, dss / GEN_DSS_PER_CSLICE, dss % GEN_DSS_PER_CSLICE); in pvc_init_mcr()
1374 icl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) in icl_gt_workarounds_init() argument
1378 icl_wa_init_mcr(gt, wal); in icl_gt_workarounds_init()
1381 wa_write_clr_set(wal, in icl_gt_workarounds_init()
1389 wa_write_or(wal, in icl_gt_workarounds_init()
1397 wa_write_or(wal, in icl_gt_workarounds_init()
1404 wa_write_or(wal, in icl_gt_workarounds_init()
1412 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE, in icl_gt_workarounds_init()
1416 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2, in icl_gt_workarounds_init()
1420 wa_mcr_write_or(wal, in icl_gt_workarounds_init()
1427 wa_write_or(wal, in icl_gt_workarounds_init()
1435 wa_mcr_write_clr(wal, GEN10_DFR_RATIO_EN_AND_CHICKEN, DFR_DISABLE); in icl_gt_workarounds_init()
1445 wa_14011060649(struct intel_gt *gt, struct i915_wa_list *wal) in wa_14011060649() argument
1455 wa_write_or(wal, VDBOX_CGCTL3F10(engine->mmio_base), in wa_14011060649()
1461 gen12_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) in gen12_gt_workarounds_init() argument
1463 icl_wa_init_mcr(gt, wal); in gen12_gt_workarounds_init()
1466 wa_14011060649(gt, wal); in gen12_gt_workarounds_init()
1469 wa_mcr_write_or(wal, GEN10_DFR_RATIO_EN_AND_CHICKEN, DFR_DISABLE); in gen12_gt_workarounds_init()
1473 tgl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) in tgl_gt_workarounds_init() argument
1477 gen12_gt_workarounds_init(gt, wal); in tgl_gt_workarounds_init()
1481 wa_mcr_write_or(wal, in tgl_gt_workarounds_init()
1487 wa_write_or(wal, in tgl_gt_workarounds_init()
1493 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2, in tgl_gt_workarounds_init()
1498 dg1_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) in dg1_gt_workarounds_init() argument
1502 gen12_gt_workarounds_init(gt, wal); in dg1_gt_workarounds_init()
1506 wa_write_or(wal, in dg1_gt_workarounds_init()
1512 wa_mcr_write_or(wal, in dg1_gt_workarounds_init()
1519 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2, in dg1_gt_workarounds_init()
1524 xehpsdv_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) in xehpsdv_gt_workarounds_init() argument
1528 xehp_init_mcr(gt, wal); in xehpsdv_gt_workarounds_init()
1531 wa_mcr_write_or(wal, SCCGCTL94DC, CG3DDISURB); in xehpsdv_gt_workarounds_init()
1535 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE, in xehpsdv_gt_workarounds_init()
1540 wa_write_or(wal, UNSLCGCTL9440, GAMTLBOACS_CLKGATE_DIS | in xehpsdv_gt_workarounds_init()
1552 wa_write_or(wal, UNSLCGCTL9444, GAMTLBGFXA0_CLKGATE_DIS | in xehpsdv_gt_workarounds_init()
1571 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE, VFUNIT_CLKGATE_DIS); in xehpsdv_gt_workarounds_init()
1574 wa_14011060649(gt, wal); in xehpsdv_gt_workarounds_init()
1577 wa_mcr_write_or(wal, XEHP_MERT_MOD_CTRL, FORCE_MISS_FTLB); in xehpsdv_gt_workarounds_init()
1580 wa_mcr_write_or(wal, XEHP_GAMCNTRL_CTRL, in xehpsdv_gt_workarounds_init()
1585 dg2_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) in dg2_gt_workarounds_init() argument
1590 xehp_init_mcr(gt, wal); in dg2_gt_workarounds_init()
1593 wa_14011060649(gt, wal); in dg2_gt_workarounds_init()
1608 wa_write_or(wal, VDBOX_CGCTL3F18(engine->mmio_base), in dg2_gt_workarounds_init()
1614 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE, in dg2_gt_workarounds_init()
1618 wa_mcr_write_or(wal, GEN11_SUBSLICE_UNIT_LEVEL_CLKGATE, in dg2_gt_workarounds_init()
1625 wa_mcr_write_or(wal, XEHP_MERT_MOD_CTRL, FORCE_MISS_FTLB); in dg2_gt_workarounds_init()
1630 wa_write_or(wal, UNSLCGCTL9430, MSQDUNIT_CLKGATE_DIS); in dg2_gt_workarounds_init()
1633 wa_write_or(wal, UNSLCGCTL9444, LTCDD_CLKGATE_DIS); in dg2_gt_workarounds_init()
1636 wa_mcr_write_or(wal, XEHP_SLICE_UNIT_LEVEL_CLKGATE, NODEDSS_CLKGATE_DIS); in dg2_gt_workarounds_init()
1639 wa_write_or(wal, UNSLCGCTL9440, GAMTLBOACS_CLKGATE_DIS | in dg2_gt_workarounds_init()
1651 wa_write_or(wal, UNSLCGCTL9444, GAMTLBGFXA0_CLKGATE_DIS | in dg2_gt_workarounds_init()
1668 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE, in dg2_gt_workarounds_init()
1672 wa_mcr_write_or(wal, SSMCGCTL9530, RTFUNIT_CLKGATE_DIS); in dg2_gt_workarounds_init()
1675 wa_mcr_write_or(wal, XEHP_GAMSTLB_CTRL, in dg2_gt_workarounds_init()
1682 wa_mcr_write_clr(wal, SARB_CHICKEN1, COMP_CKN_IN); in dg2_gt_workarounds_init()
1689 wa_mcr_write_or(wal, XEHP_SQCM, EN_32B_ACCESS); in dg2_gt_workarounds_init()
1692 wa_write_clr(wal, GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE); in dg2_gt_workarounds_init()
1695 wa_mcr_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB); in dg2_gt_workarounds_init()
1696 wa_mcr_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB); in dg2_gt_workarounds_init()
1697 wa_mcr_write_or(wal, XEHP_VDBX_MOD_CTRL, FORCE_MISS_FTLB); in dg2_gt_workarounds_init()
1698 wa_mcr_write_or(wal, XEHP_VEBX_MOD_CTRL, FORCE_MISS_FTLB); in dg2_gt_workarounds_init()
1701 wa_mcr_write_or(wal, XEHP_GAMCNTRL_CTRL, in dg2_gt_workarounds_init()
1706 pvc_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) in pvc_gt_workarounds_init() argument
1708 pvc_init_mcr(gt, wal); in pvc_gt_workarounds_init()
1711 wa_write_clr(wal, GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE); in pvc_gt_workarounds_init()
1714 wa_mcr_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB); in pvc_gt_workarounds_init()
1715 wa_mcr_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB); in pvc_gt_workarounds_init()
1716 wa_mcr_write_or(wal, XEHP_VDBX_MOD_CTRL, FORCE_MISS_FTLB); in pvc_gt_workarounds_init()
1717 wa_mcr_write_or(wal, XEHP_VEBX_MOD_CTRL, FORCE_MISS_FTLB); in pvc_gt_workarounds_init()
1721 xelpg_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) in xelpg_gt_workarounds_init() argument
1726 wa_mcr_write_clr(wal, SARB_CHICKEN1, COMP_CKN_IN); in xelpg_gt_workarounds_init()
1729 wa_mcr_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB); in xelpg_gt_workarounds_init()
1730 wa_mcr_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB); in xelpg_gt_workarounds_init()
1741 xelpmp_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) in xelpmp_gt_workarounds_init() argument
1750 wa_write_or(wal, XELPMP_GSC_MOD_CTRL, FORCE_MISS_FTLB); in xelpmp_gt_workarounds_init()
1751 wa_write_or(wal, XELPMP_VDBX_MOD_CTRL, FORCE_MISS_FTLB); in xelpmp_gt_workarounds_init()
1752 wa_write_or(wal, XELPMP_VEBX_MOD_CTRL, FORCE_MISS_FTLB); in xelpmp_gt_workarounds_init()
1759 gt_init_workarounds(struct intel_gt *gt, struct i915_wa_list *wal) in gt_init_workarounds() argument
1765 xelpmp_gt_workarounds_init(gt, wal); in gt_init_workarounds()
1773 xelpg_gt_workarounds_init(gt, wal); in gt_init_workarounds()
1775 pvc_gt_workarounds_init(gt, wal); in gt_init_workarounds()
1777 dg2_gt_workarounds_init(gt, wal); in gt_init_workarounds()
1779 xehpsdv_gt_workarounds_init(gt, wal); in gt_init_workarounds()
1781 dg1_gt_workarounds_init(gt, wal); in gt_init_workarounds()
1783 tgl_gt_workarounds_init(gt, wal); in gt_init_workarounds()
1785 gen12_gt_workarounds_init(gt, wal); in gt_init_workarounds()
1787 icl_gt_workarounds_init(gt, wal); in gt_init_workarounds()
1789 cfl_gt_workarounds_init(gt, wal); in gt_init_workarounds()
1791 glk_gt_workarounds_init(gt, wal); in gt_init_workarounds()
1793 kbl_gt_workarounds_init(gt, wal); in gt_init_workarounds()
1795 gen9_gt_workarounds_init(gt, wal); in gt_init_workarounds()
1797 skl_gt_workarounds_init(gt, wal); in gt_init_workarounds()
1799 hsw_gt_workarounds_init(gt, wal); in gt_init_workarounds()
1801 vlv_gt_workarounds_init(gt, wal); in gt_init_workarounds()
1803 ivb_gt_workarounds_init(gt, wal); in gt_init_workarounds()
1805 snb_gt_workarounds_init(gt, wal); in gt_init_workarounds()
1807 ilk_gt_workarounds_init(gt, wal); in gt_init_workarounds()
1809 g4x_gt_workarounds_init(gt, wal); in gt_init_workarounds()
1811 gen4_gt_workarounds_init(gt, wal); in gt_init_workarounds()
1820 struct i915_wa_list *wal = >->wa_list; in intel_gt_init_workarounds() local
1822 wa_init_start(wal, gt, "GT", "global"); in intel_gt_init_workarounds()
1823 gt_init_workarounds(gt, wal); in intel_gt_init_workarounds()
1824 wa_init_finish(wal); in intel_gt_init_workarounds()
1828 wal_get_fw_for_rmw(struct intel_uncore *uncore, const struct i915_wa_list *wal) in wal_get_fw_for_rmw() argument
1834 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) in wal_get_fw_for_rmw()
1859 static void wa_list_apply(const struct i915_wa_list *wal) in wa_list_apply() argument
1861 struct intel_gt *gt = wal->gt; in wa_list_apply()
1868 if (!wal->count) in wa_list_apply()
1871 fw = wal_get_fw_for_rmw(uncore, wal); in wa_list_apply()
1877 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { in wa_list_apply()
1898 wa_verify(gt, wa, val, wal->name, "application"); in wa_list_apply()
1913 const struct i915_wa_list *wal, in wa_list_verify() argument
1923 fw = wal_get_fw_for_rmw(uncore, wal); in wa_list_verify()
1929 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) in wa_list_verify()
1930 ok &= wa_verify(wal->gt, wa, wa->is_mcr ? in wa_list_verify()
1933 wal->name, from); in wa_list_verify()
1963 whitelist_reg_ext(struct i915_wa_list *wal, i915_reg_t reg, u32 flags) in whitelist_reg_ext() argument
1969 if (GEM_DEBUG_WARN_ON(wal->count >= RING_MAX_NONPRIV_SLOTS)) in whitelist_reg_ext()
1976 _wa_add(wal, &wa); in whitelist_reg_ext()
1980 whitelist_mcr_reg_ext(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 flags) in whitelist_mcr_reg_ext() argument
1987 if (GEM_DEBUG_WARN_ON(wal->count >= RING_MAX_NONPRIV_SLOTS)) in whitelist_mcr_reg_ext()
1994 _wa_add(wal, &wa); in whitelist_mcr_reg_ext()
1998 whitelist_reg(struct i915_wa_list *wal, i915_reg_t reg) in whitelist_reg() argument
2000 whitelist_reg_ext(wal, reg, RING_FORCE_TO_NONPRIV_ACCESS_RW); in whitelist_reg()
2004 whitelist_mcr_reg(struct i915_wa_list *wal, i915_mcr_reg_t reg) in whitelist_mcr_reg() argument
2006 whitelist_mcr_reg_ext(wal, reg, RING_FORCE_TO_NONPRIV_ACCESS_RW); in whitelist_mcr_reg()
2317 const struct i915_wa_list *wal = &engine->whitelist; in intel_engine_apply_whitelist() local
2323 if (!wal->count) in intel_engine_apply_whitelist()
2326 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) in intel_engine_apply_whitelist()
2346 engine_fake_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) in engine_fake_wa_init() argument
2375 wa_masked_field_set(wal, in engine_fake_wa_init()
2389 rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) in rcs_engine_wa_init() argument
2396 wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS, in rcs_engine_wa_init()
2405 wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE, in rcs_engine_wa_init()
2413 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2, in rcs_engine_wa_init()
2419 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2, GEN12_ENABLE_LARGE_GRF_MODE); in rcs_engine_wa_init()
2425 wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN4, in rcs_engine_wa_init()
2432 wa_masked_dis(wal, GEN12_CS_DEBUG_MODE1_CCCSUNIT_BE_COMMON, in rcs_engine_wa_init()
2442 wa_mcr_masked_dis(wal, XEHP_HDC_CHICKEN0, in rcs_engine_wa_init()
2451 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN, in rcs_engine_wa_init()
2457 wa_mcr_masked_en(wal, in rcs_engine_wa_init()
2462 wa_mcr_write_or(wal, XEHP_L3NODEARBCFG, XEHP_LNESPARE); in rcs_engine_wa_init()
2468 wa_mcr_write_or(wal, RT_CTRL, DIS_NULL_QUERY); in rcs_engine_wa_init()
2473 wa_mcr_masked_en(wal, GEN9_HALF_SLICE_CHICKEN7, in rcs_engine_wa_init()
2479 wa_mcr_add(wal, GEN10_CACHE_MODE_SS, 0, in rcs_engine_wa_init()
2491 wa_write_or(wal, in rcs_engine_wa_init()
2501 wa_write_or(wal, in rcs_engine_wa_init()
2509 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2, GEN12_DISABLE_EARLY_READ); in rcs_engine_wa_init()
2517 wa_write_or(wal, GEN7_FF_THREAD_MODE, in rcs_engine_wa_init()
2529 wa_masked_en(wal, in rcs_engine_wa_init()
2538 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2, in rcs_engine_wa_init()
2545 wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN4, GEN12_DISABLE_TDL_PUSH); in rcs_engine_wa_init()
2560 wa_masked_en(wal, in rcs_engine_wa_init()
2569 wa_mcr_masked_en(wal, in rcs_engine_wa_init()
2576 wa_masked_en(wal, in rcs_engine_wa_init()
2584 wa_write_or(wal, in rcs_engine_wa_init()
2592 wa_write_clr_set(wal, in rcs_engine_wa_init()
2596 wa_write_clr_set(wal, in rcs_engine_wa_init()
2605 wa_mcr_write_or(wal, in rcs_engine_wa_init()
2610 wa_write_or(wal, in rcs_engine_wa_init()
2615 wa_mcr_write_clr_set(wal, in rcs_engine_wa_init()
2621 wa_masked_en(wal, GEN9_CSFE_CHICKEN1_RCS, in rcs_engine_wa_init()
2628 wa_write_or(wal, in rcs_engine_wa_init()
2633 wa_masked_en(wal, in rcs_engine_wa_init()
2693 wa_masked_en(wal, in rcs_engine_wa_init()
2702 wa_write_or(wal, in rcs_engine_wa_init()
2709 wa_masked_en(wal, in rcs_engine_wa_init()
2716 wa_masked_en(wal, in rcs_engine_wa_init()
2721 wa_mcr_write_or(wal, in rcs_engine_wa_init()
2727 wa_mcr_write_clr_set(wal, in rcs_engine_wa_init()
2734 wa_mcr_write_or(wal, in rcs_engine_wa_init()
2739 wa_write_clr_set(wal, GEN9_SCRATCH_LNCF1, in rcs_engine_wa_init()
2741 wa_mcr_write_clr_set(wal, GEN8_L3SQCREG4, in rcs_engine_wa_init()
2743 wa_mcr_write_clr_set(wal, GEN9_SCRATCH1, in rcs_engine_wa_init()
2749 wa_masked_en(wal, in rcs_engine_wa_init()
2752 wa_masked_dis(wal, in rcs_engine_wa_init()
2760 wa_masked_en(wal, in rcs_engine_wa_init()
2770 wa_write_clr_set(wal, in rcs_engine_wa_init()
2779 wa_masked_en(wal, in rcs_engine_wa_init()
2787 wa_masked_en(wal, in rcs_engine_wa_init()
2793 wa_masked_dis(wal, in rcs_engine_wa_init()
2804 wa_write_clr_set(wal, in rcs_engine_wa_init()
2813 wa_masked_en(wal, in rcs_engine_wa_init()
2820 wa_masked_en(wal, in rcs_engine_wa_init()
2825 wa_masked_dis(wal, CACHE_MODE_0_GEN7, RC_OP_FLUSH_ENABLE); in rcs_engine_wa_init()
2832 wa_masked_en(wal, in rcs_engine_wa_init()
2844 wa_masked_field_set(wal, in rcs_engine_wa_init()
2858 wa_masked_en(wal, in rcs_engine_wa_init()
2868 wa_masked_en(wal, in rcs_engine_wa_init()
2873 wa_masked_en(wal, in rcs_engine_wa_init()
2877 wa_masked_en(wal, in rcs_engine_wa_init()
2897 wa_masked_field_set(wal, in rcs_engine_wa_init()
2903 wa_masked_dis(wal, CACHE_MODE_0, RC_OP_FLUSH_ENABLE); in rcs_engine_wa_init()
2911 wa_masked_dis(wal, in rcs_engine_wa_init()
2918 wa_add(wal, RING_MI_MODE(RENDER_RING_BASE), in rcs_engine_wa_init()
2934 wa_add(wal, ECOSKPD(RENDER_RING_BASE), in rcs_engine_wa_init()
2941 xcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) in xcs_engine_wa_init() argument
2947 wa_write(wal, in xcs_engine_wa_init()
2954 ccs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) in ccs_engine_wa_init() argument
2958 wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS, DISABLE_ECC); in ccs_engine_wa_init()
2976 struct i915_wa_list *wal) in add_render_compute_tuning_settings() argument
2979 wa_mcr_write(wal, XEHPC_L3SCRUB, in add_render_compute_tuning_settings()
2981 wa_mcr_masked_en(wal, XEHPC_LNCFMISCCFGREG0, XEHPC_HOSTCACHEEN); in add_render_compute_tuning_settings()
2985 wa_mcr_write_or(wal, XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS); in add_render_compute_tuning_settings()
2986 wa_mcr_write_clr_set(wal, RT_CTRL, STACKID_CTRL, STACKID_CTRL_512); in add_render_compute_tuning_settings()
2995 wa_mcr_masked_field_set(wal, GEN9_ROW_CHICKEN4, THREAD_EX_ARB_MODE, in add_render_compute_tuning_settings()
2999 wa_write_clr(wal, GEN8_GARBCNTL, GEN12_BUS_HASH_CTL_BIT_EXC); in add_render_compute_tuning_settings()
3012 general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) in general_render_compute_wa_init() argument
3016 add_render_compute_tuning_settings(i915, wal); in general_render_compute_wa_init()
3023 wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW, in general_render_compute_wa_init()
3032 wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE); in general_render_compute_wa_init()
3039 wa_masked_en(wal, VFG_PREEMPTION_CHICKEN, POLYGON_TRIFAN_LINELOOP_DISABLE); in general_render_compute_wa_init()
3048 wa_mcr_write_clr_set(wal, LSC_CHICKEN_BIT_0_UDW, in general_render_compute_wa_init()
3053 wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0, in general_render_compute_wa_init()
3064 wa_mcr_add(wal, LSC_CHICKEN_BIT_0_UDW, 0, in general_render_compute_wa_init()
3071 wa_mcr_masked_en(wal, XEHPC_LNCFMISCCFGREG0, XEHPC_OVRLSCCC); in general_render_compute_wa_init()
3076 wa_mcr_masked_en(wal, in general_render_compute_wa_init()
3081 wa_mcr_masked_en(wal, in general_render_compute_wa_init()
3086 wa_mcr_write_or(wal, XEHP_L3NODEARBCFG, XEHP_LNESPARE); in general_render_compute_wa_init()
3089 wa_mcr_masked_en(wal, GEN8_HALF_SLICE_CHICKEN1, in general_render_compute_wa_init()
3094 wa_mcr_masked_dis(wal, MLTICTXCTL, TDONRENDER); in general_render_compute_wa_init()
3095 wa_mcr_write_or(wal, L3SQCREG1_CCS0, FLUSHALLNONCOH); in general_render_compute_wa_init()
3101 wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE); in general_render_compute_wa_init()
3104 wa_masked_en(wal, FF_SLICE_CS_CHICKEN2, GEN12_PERF_FIX_BALANCING_CFE_DISABLE); in general_render_compute_wa_init()
3112 wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8); in general_render_compute_wa_init()
3123 wa_mcr_add(wal, GEN10_CACHE_MODE_SS, 0, in general_render_compute_wa_init()
3130 engine_init_workarounds(struct intel_engine_cs *engine, struct i915_wa_list *wal) in engine_init_workarounds() argument
3135 engine_fake_wa_init(engine, wal); in engine_init_workarounds()
3143 general_render_compute_wa_init(engine, wal); in engine_init_workarounds()
3146 ccs_engine_wa_init(engine, wal); in engine_init_workarounds()
3148 rcs_engine_wa_init(engine, wal); in engine_init_workarounds()
3150 xcs_engine_wa_init(engine, wal); in engine_init_workarounds()
3155 struct i915_wa_list *wal = &engine->wa_list; in intel_engine_init_workarounds() local
3157 wa_init_start(wal, engine->gt, "engine", engine->name); in intel_engine_init_workarounds()
3158 engine_init_workarounds(engine, wal); in intel_engine_init_workarounds()
3159 wa_init_finish(wal); in intel_engine_init_workarounds()
3231 const struct i915_wa_list *wal, in wa_list_srm() argument
3243 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { in wa_list_srm()
3252 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { in wa_list_srm()
3269 const struct i915_wa_list * const wal, in engine_wa_list_verify() argument
3280 if (!wal->count) in engine_wa_list_verify()
3284 wal->count * sizeof(u32)); in engine_wa_list_verify()
3310 err = wa_list_srm(rq, wal, vma); in engine_wa_list_verify()
3332 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { in engine_wa_list_verify()
3336 if (!wa_verify(wal->gt, wa, results[i], wal->name, from)) in engine_wa_list_verify()