Lines Matching refs:plane
204 struct intel_vgpu_primary_plane_format *plane) in intel_vgpu_decode_primary_plane() argument
215 plane->enabled = !!(val & DISP_ENABLE); in intel_vgpu_decode_primary_plane()
216 if (!plane->enabled) in intel_vgpu_decode_primary_plane()
220 plane->tiled = val & PLANE_CTL_TILED_MASK; in intel_vgpu_decode_primary_plane()
232 plane->bpp = skl_pixel_formats[fmt].bpp; in intel_vgpu_decode_primary_plane()
233 plane->drm_format = skl_pixel_formats[fmt].drm_format; in intel_vgpu_decode_primary_plane()
235 plane->tiled = val & DISP_TILED; in intel_vgpu_decode_primary_plane()
237 plane->bpp = bdw_pixel_formats[fmt].bpp; in intel_vgpu_decode_primary_plane()
238 plane->drm_format = bdw_pixel_formats[fmt].drm_format; in intel_vgpu_decode_primary_plane()
241 if (!plane->bpp) { in intel_vgpu_decode_primary_plane()
246 plane->hw_format = fmt; in intel_vgpu_decode_primary_plane()
248 plane->base = vgpu_vreg_t(vgpu, DSPSURF(pipe)) & I915_GTT_PAGE_MASK; in intel_vgpu_decode_primary_plane()
249 if (!vgpu_gmadr_is_valid(vgpu, plane->base)) in intel_vgpu_decode_primary_plane()
252 plane->base_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm, plane->base); in intel_vgpu_decode_primary_plane()
253 if (plane->base_gpa == INTEL_GVT_INVALID_ADDR) { in intel_vgpu_decode_primary_plane()
255 plane->base); in intel_vgpu_decode_primary_plane()
259 plane->stride = intel_vgpu_get_stride(vgpu, pipe, plane->tiled, in intel_vgpu_decode_primary_plane()
262 _PRI_PLANE_STRIDE_MASK, plane->bpp); in intel_vgpu_decode_primary_plane()
264 plane->width = (vgpu_vreg_t(vgpu, PIPESRC(pipe)) & _PIPE_H_SRCSZ_MASK) >> in intel_vgpu_decode_primary_plane()
266 plane->width += 1; in intel_vgpu_decode_primary_plane()
267 plane->height = (vgpu_vreg_t(vgpu, PIPESRC(pipe)) & in intel_vgpu_decode_primary_plane()
269 plane->height += 1; /* raw height is one minus the real value */ in intel_vgpu_decode_primary_plane()
272 plane->x_offset = (val & _PRI_PLANE_X_OFF_MASK) >> in intel_vgpu_decode_primary_plane()
274 plane->y_offset = (val & _PRI_PLANE_Y_OFF_MASK) >> in intel_vgpu_decode_primary_plane()
334 struct intel_vgpu_cursor_plane_format *plane) in intel_vgpu_decode_cursor_plane() argument
347 plane->enabled = (mode != MCURSOR_MODE_DISABLE); in intel_vgpu_decode_cursor_plane()
348 if (!plane->enabled) in intel_vgpu_decode_cursor_plane()
357 plane->mode = mode; in intel_vgpu_decode_cursor_plane()
358 plane->bpp = cursor_pixel_formats[index].bpp; in intel_vgpu_decode_cursor_plane()
359 plane->drm_format = cursor_pixel_formats[index].drm_format; in intel_vgpu_decode_cursor_plane()
360 plane->width = cursor_pixel_formats[index].width; in intel_vgpu_decode_cursor_plane()
361 plane->height = cursor_pixel_formats[index].height; in intel_vgpu_decode_cursor_plane()
371 plane->base = vgpu_vreg_t(vgpu, CURBASE(pipe)) & I915_GTT_PAGE_MASK; in intel_vgpu_decode_cursor_plane()
372 if (!vgpu_gmadr_is_valid(vgpu, plane->base)) in intel_vgpu_decode_cursor_plane()
375 plane->base_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm, plane->base); in intel_vgpu_decode_cursor_plane()
376 if (plane->base_gpa == INTEL_GVT_INVALID_ADDR) { in intel_vgpu_decode_cursor_plane()
378 plane->base); in intel_vgpu_decode_cursor_plane()
383 plane->x_pos = (val & _CURSOR_POS_X_MASK) >> _CURSOR_POS_X_SHIFT; in intel_vgpu_decode_cursor_plane()
384 plane->x_sign = (val & _CURSOR_SIGN_X_MASK) >> _CURSOR_SIGN_X_SHIFT; in intel_vgpu_decode_cursor_plane()
385 plane->y_pos = (val & _CURSOR_POS_Y_MASK) >> _CURSOR_POS_Y_SHIFT; in intel_vgpu_decode_cursor_plane()
386 plane->y_sign = (val & _CURSOR_SIGN_Y_MASK) >> _CURSOR_SIGN_Y_SHIFT; in intel_vgpu_decode_cursor_plane()
388 plane->x_hot = vgpu_vreg_t(vgpu, vgtif_reg(cursor_x_hot)); in intel_vgpu_decode_cursor_plane()
389 plane->y_hot = vgpu_vreg_t(vgpu, vgtif_reg(cursor_y_hot)); in intel_vgpu_decode_cursor_plane()
413 struct intel_vgpu_sprite_plane_format *plane) in intel_vgpu_decode_sprite_plane() argument
425 plane->enabled = !!(val & SPRITE_ENABLE); in intel_vgpu_decode_sprite_plane()
426 if (!plane->enabled) in intel_vgpu_decode_sprite_plane()
429 plane->tiled = !!(val & SPRITE_TILED); in intel_vgpu_decode_sprite_plane()
439 plane->hw_format = fmt; in intel_vgpu_decode_sprite_plane()
440 plane->bpp = sprite_pixel_formats[fmt].bpp; in intel_vgpu_decode_sprite_plane()
473 plane->drm_format = drm_format; in intel_vgpu_decode_sprite_plane()
475 plane->base = vgpu_vreg_t(vgpu, SPRSURF(pipe)) & I915_GTT_PAGE_MASK; in intel_vgpu_decode_sprite_plane()
476 if (!vgpu_gmadr_is_valid(vgpu, plane->base)) in intel_vgpu_decode_sprite_plane()
479 plane->base_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm, plane->base); in intel_vgpu_decode_sprite_plane()
480 if (plane->base_gpa == INTEL_GVT_INVALID_ADDR) { in intel_vgpu_decode_sprite_plane()
482 plane->base); in intel_vgpu_decode_sprite_plane()
486 plane->stride = vgpu_vreg_t(vgpu, SPRSTRIDE(pipe)) & in intel_vgpu_decode_sprite_plane()
490 plane->height = (val & _SPRITE_SIZE_HEIGHT_MASK) >> in intel_vgpu_decode_sprite_plane()
492 plane->width = (val & _SPRITE_SIZE_WIDTH_MASK) >> in intel_vgpu_decode_sprite_plane()
494 plane->height += 1; /* raw height is one minus the real value */ in intel_vgpu_decode_sprite_plane()
495 plane->width += 1; /* raw width is one minus the real value */ in intel_vgpu_decode_sprite_plane()
498 plane->x_pos = (val & _SPRITE_POS_X_MASK) >> _SPRITE_POS_X_SHIFT; in intel_vgpu_decode_sprite_plane()
499 plane->y_pos = (val & _SPRITE_POS_Y_MASK) >> _SPRITE_POS_Y_SHIFT; in intel_vgpu_decode_sprite_plane()
502 plane->x_offset = (val & _SPRITE_OFFSET_START_X_MASK) >> in intel_vgpu_decode_sprite_plane()
504 plane->y_offset = (val & _SPRITE_OFFSET_START_Y_MASK) >> in intel_vgpu_decode_sprite_plane()